On Wed, Jan 15, 2020 at 8:51 PM Li, Dennis <Dennis.Li@xxxxxxx> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi, Alex,
> it is better to refine the patch as a common function, not only used for raven.
I originally had the name as gfx_v9_0_check_disable_gfxoff(), but I
changed it to be raven specific because if we call this independent of
the other conditions in the CHIP_RAVEN case, we may end up disabling
gfxoff in cases where we don't want to (e.g., if a raven1 refresh uses
the same DID/SSID/RIDs as a non-kicker for example, and one works and
the other doesn't). I guess we can revisit if we have to add cases
for other asics. If you feel strongly I can change the name.
Alex
>
> Best Regards
> Dennis Li
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex Deucher
> Sent: Thursday, January 16, 2020 1:32 AM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>
> Subject: [PATCH] drm/amdgpu: attempt to enable gfxoff on more raven1 boards
>
> Switch to a blacklist so we can disable specific boards that are problematic.
>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 42 ++++++++++++++++++++++++---
> 1 file changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index e3d466bd5c4e..b48b07bcd0fb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1031,6 +1031,37 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
> }
> }
>
> +struct amdgpu_gfxoff_quirk {
> + u16 chip_vendor;
> + u16 chip_device;
> + u16 subsys_vendor;
> + u16 subsys_device;
> + u8 revision;
> +};
> +
> +static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = {
> + /* https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.kernel.org%2Fshow_bug.cgi%3Fid%3D204689&data=02%7C01%7CDennis.Li%40amd.com%7C33990b7157714a2f943a08d799e0cda3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637147063123345220&sdata=2mT3Eug%2FEDKGGbI1bqymp2tnMqLX4x%2B2BAWnLUnq5m0%3D&reserved=0 */
> + { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
> + { 0, 0, 0, 0, 0 },
> +};
> +
> +static bool gfx_v9_0_raven_check_disable_gfxoff(struct pci_dev *pdev) {
> + const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list;
> +
> + while (p && p->chip_device != 0) {
> + if (pdev->vendor == p->chip_vendor &&
> + pdev->device == p->chip_device &&
> + pdev->subsystem_vendor == p->subsys_vendor &&
> + pdev->subsystem_device == p->subsys_device &&
> + pdev->revision == p->revision) {
> + return true;
> + }
> + ++p;
> + }
> + return false;
> +}
> +
> static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) {
> switch (adev->asic_type) {
> @@ -1039,10 +1070,13 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
> case CHIP_VEGA20:
> break;
> case CHIP_RAVEN:
> - if (!(adev->rev_id >= 0x8 ||
> - adev->pdev->device == 0x15d8) &&
> - (adev->pm.fw_version < 0x41e2b || /* not raven1 fresh */
> - !adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore ucodes */
> + if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) &&
> + ((adev->gfx.rlc_fw_version != 106 &&
> + adev->gfx.rlc_fw_version < 531) ||
> + (adev->gfx.rlc_fw_version == 53815) ||
> + (adev->gfx.rlc_feature_version < 1) ||
> + !adev->gfx.rlc.is_rlc_v2_1) &&
> + !gfx_v9_0_raven_check_disable_gfxoff(adev->pdev))
> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>
> if (adev->pm.pp_feature & PP_GFXOFF_MASK)
> --
> 2.24.1
>
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