On Mon, Jan 13, 2020 at 06:16:22PM +0800, chen gong wrote: > Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to > hang when GPU is in "gfxoff" state. > > Signed-off-by: chen gong <curry.gong@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index e3d466b..a666086 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -4702,7 +4702,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) > *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; > > /* AMD_CG_SUPPORT_GFX_CP_LS */ > - data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); > + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); We should use kiq instead of mmio access for the whole gfx_v9_0_get_clockgating_state(). Thanks, Ray > if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) > *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; > > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cray.huang%40amd.com%7Cc8b2a8c2091f4336ee5708d79811af07%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637145074034487948&sdata=emUuTvGn3FGbQGrIs%2FkoR3d0YAQYvHUjBqA5cYlkL2g%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
