On Wed, Jan 8, 2020 at 11:17 AM Hawking Zhang <Hawking.Zhang@xxxxxxx> wrote:
>
> query_ras_error_count function will be invoked to query
> single bit error count detected in sdma ip block
>
> Change-Id: I1b17df7c66e71739ae4c31900bd96c5359af2240
> Signed-off-by: Hawking Zhang <Hawking.Zhang@xxxxxxx>
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 6 +
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 163 +++++++++++++++++++++++
> 2 files changed, 169 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> index 957791673fcd..9e87a97f81fb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> @@ -50,6 +50,11 @@ struct amdgpu_sdma_instance {
> bool burst_nop;
> };
>
> +struct amdgpu_sdma_ras_funcs {
> + int (*query_ras_error_count)(struct amdgpu_device *adev,
> + uint32_t instance, void *ras_error_status);
> +};
> +
> struct amdgpu_sdma {
> struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
> struct drm_gpu_scheduler *sdma_sched[AMDGPU_MAX_SDMA_INSTANCES];
> @@ -61,6 +66,7 @@ struct amdgpu_sdma {
> uint32_t srbm_soft_reset;
> bool has_page_queue;
> struct ras_common_if *ras_if;
> + const struct amdgpu_sdma_ras_funcs *funcs;
> };
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 4074314695c3..a00b85934b04 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -82,6 +82,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
> static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
> static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
> static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
> +static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
>
> static const struct soc15_reg_golden golden_settings_sdma_4[] = {
> SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
> @@ -257,6 +258,105 @@ static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
> SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
> };
>
> +static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
> + { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
> + 0, 0,
> + },
> + { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
> + 0, 0,
> + },
> + { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
> + 0, 0,
> + },
> + { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
> + 0, 0,
> + },
> + { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
> + 0, 0,
> + },
> + { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
> + 0, 0,
> + },
> + { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
> + 0, 0,
> + },
> + { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
> + 0, 0,
> + },
> + { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
> + SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
> + 0, 0,
> + },
> +};
> +
> static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
> u32 instance, u32 offset)
> {
> @@ -1687,6 +1787,7 @@ static int sdma_v4_0_early_init(void *handle)
> sdma_v4_0_set_buffer_funcs(adev);
> sdma_v4_0_set_vm_pte_funcs(adev);
> sdma_v4_0_set_irq_funcs(adev);
> + sdma_v4_0_set_ras_funcs(adev);
>
> return 0;
> }
> @@ -2417,6 +2518,68 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
> adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> }
>
> +static void sdma_v4_0_get_ras_error_count(uint32_t value,
> + uint32_t instance,
> + uint32_t *sec_count)
> +{
> + uint32_t i;
> + uint32_t sec_cnt;
> +
> + /* double bits error (multiple bits) error detection is not supported */
> + for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
> + /* the SDMA_EDC_COUNTER register in each sdma instance
> + * shares the same sed shift_mask
> + * */
> + sec_cnt = (value &
> + sdma_v4_0_ras_fields[i].sec_count_mask) >>
> + sdma_v4_0_ras_fields[i].sec_count_shift;
> + if (sec_cnt) {
> + DRM_INFO("Detected %s in SDMA%d, SED %d\n",
> + sdma_v4_0_ras_fields[i].name,
> + instance, sec_cnt);
> + *sec_count += sec_cnt;
> + }
> + }
> +}
> +
> +static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
> + uint32_t instance, void *ras_error_status)
> +{
> + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
> + uint32_t sec_count = 0;
> + uint32_t reg_value = 0;
> +
> + reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
> + /* double bit error is not supported */
> + if (reg_value)
> + sdma_v4_0_get_ras_error_count(reg_value,
> + instance, &sec_count);
> + /* err_data->ce_count should be initialized to 0
> + * before calling into this function */
> + err_data->ce_count += sec_count;
> + /* double bit error is not supported
> + * set ue count to 0 */
> + err_data->ue_count = 0;
> +
> + return 0;
> +};
> +
> +static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
> + .query_ras_error_count = sdma_v4_0_query_ras_error_count,
> +};
> +
> +static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
> +{
> + switch (adev->asic_type) {
> + case CHIP_VEGA20:
> + case CHIP_ARCTURUS:
> + adev->sdma.funcs = &sdma_v4_0_ras_funcs;
> + break;
> + default:
> + break;
> + }
> +}
> +
> const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
> .type = AMD_IP_BLOCK_TYPE_SDMA,
> .major = 4,
> --
> 2.17.1
>
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