RE: [PATCH] drm/amdgpu: resolved bug in UMC RAS CE query

["Clements, John" <John.Clements@xxxxxxx>]

[AMD Official Use Only - Internal Distribution Only]

 

Not necessary, but I wanted to make the register all access’ consistent.

 

In a future patch I shall replace the MMIO register offsets with the SMN offsets directly instead of having *4 all over the place.

 

Thank you,

John Clements

 

From: Zhou1, Tao <Tao.Zhou1@xxxxxxx>
Sent: Tuesday, January 7, 2020 1:59 PM
To: Clements, John <John.Clements@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx; dl.srdc_lnx_ras <dl.srdc_lnx_ras@xxxxxxx>
Subject: RE: [PATCH] drm/amdgpu: resolved bug in UMC RAS CE query

 

[AMD Official Use Only - Internal Distribution Only]

 

Reviewed-by: Tao Zhou <tao.zhou1@xxxxxxx>

 

BTW, are you sure replacing RREG32/WREG32 with RREG32/WREG32_PCIE is also necessary to fix the bug?

 

Regards,

Tao

 

From: Clements, John <John.Clements@xxxxxxx>
Sent: 2020年1月7日 11:54
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; dl.srdc_lnx_ras <dl.srdc_lnx_ras@xxxxxxx>
Subject: [PATCH] drm/amdgpu: resolved bug in UMC RAS CE query

 

[AMD Official Use Only - Internal Distribution Only]

 

Submitting patch to access CE registers via SMN and disable UMC indexing mode.

 

Thank you,

John Clements

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