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[AMD Official Use Only - Internal Distribution Only]
Thanks Feifei!
From: Xu, Feifei <Feifei.Xu@xxxxxxx>
Sent: Wednesday, December 11, 2019 11:29 To: Yin, Tianci (Rico) <Tianci.Yin@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Yuan, Xiaojie <Xiaojie.Yuan@xxxxxxx>; Long, Gang <Gang.Long@xxxxxxx>; Li, Pauline <Pauline.Li@xxxxxxx>; Yin, Tianci (Rico) <Tianci.Yin@xxxxxxx> Subject: RE: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings Series is Reviewed-by: Feifei Xu <Feifei Xu@xxxxxxx> -----Original Message----- From: Tianci Yin <tianci.yin@xxxxxxx> Sent: Wednesday, December 11, 2019 11:22 AM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Zhang, Hawking <Hawking.Zhang@xxxxxxx>; Xu, Feifei <Feifei.Xu@xxxxxxx>; Yuan, Xiaojie <Xiaojie.Yuan@xxxxxxx>; Long, Gang <Gang.Long@xxxxxxx>; Li, Pauline <Pauline.Li@xxxxxxx>; Yin, Tianci (Rico) <Tianci.Yin@xxxxxxx> Subject: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings From: "Tianci.Yin" <tianci.yin@xxxxxxx> add registers: mmSPI_CONFIG_CNTL Signed-off-by: Tianci.Yin <tianci.yin@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index ed630d37c32c..f3324fa4e194 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -114,6 +114,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070104), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), -- 2.17.1 |
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