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You can have my RB on the first patch if you fix the compiler warnings.
Alex
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Zhang, Jack (Jian) <Jack.Zhang1@xxxxxxx>
Sent: Thursday, November 21, 2019 10:58 AM To: Alex Deucher <alexdeucher@xxxxxxxxx> Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Subject: Re: [PATCH 2/2] drm/amd/amdgpu/sriov skip RLCG s/r list for arcturus VF.
Thanks Alex for this review.
Both of the two patches will not influence bare-metal code path.
B. R.
Jack
From: Alex Deucher <alexdeucher@xxxxxxxxx>
Sent: Thursday, November 21, 2019 11:26:37 PM To: Zhang, Jack (Jian) <Jack.Zhang1@xxxxxxx> Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Subject: Re: [PATCH 2/2] drm/amd/amdgpu/sriov skip RLCG s/r list for arcturus VF. Nevermind. I missed the sr-iov check. Patch is:
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx> On Thu, Nov 21, 2019 at 10:25 AM Alex Deucher <alexdeucher@xxxxxxxxx> wrote: > > Won't this impact bare metal hw that needs this? > > Alex > > On Thu, Nov 21, 2019 at 1:17 AM Jack Zhang <Jack.Zhang1@xxxxxxx> wrote: > > > > After rlcg fw 2.1, kmd driver starts to load extra fw for > > LIST_CNTL,GPM_MEM,SRM_MEM. We needs to skip the three fw > > because all rlcg related fw have been loaded by host driver. > > Guest driver would load the three fw fail without this change. > > > > Signed-off-by: Jack Zhang <Jack.Zhang1@xxxxxxx> > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > > index c3a42d3..eecde80 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c > > @@ -1470,7 +1470,10 @@ static int psp_np_fw_load(struct psp_context *psp) > > || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 > > || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 > > || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 > > - || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) > > + || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G > > + || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL > > + || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM > > + || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) > > /*skip ucode loading in SRIOV VF */ > > continue; > > > > -- > > 2.7.4 > > > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > > https://nam11.safelinks.protection.outlook.com/?url=""> |
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