Hi Alex, IMHO, driver sending Disallow_Gfxoff message to SMU doesn't mean gfx block will be immediately powered up, so I'm not sure MMIO register access will be successful within this time window(maybe GRBM access will be pending until gfx block is powered up?) If you are not in a hurry to commit this fix, I can verify on my Navi boards next Monday. BR, Xiaojie > On Nov 15, 2019, at 12:44 AM, Alex Deucher <alexdeucher@xxxxxxxxx> wrote: > > When gfxoff is enabled, accessing gfx registers via MMIO > can lead to a hang. > > Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497 > Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > index 6ddea7607ad0..5f3b3a705b29 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > @@ -659,15 +659,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file > return -ENOMEM; > alloc_size = info->read_mmr_reg.count * sizeof(*regs); > > - for (i = 0; i < info->read_mmr_reg.count; i++) > + amdgpu_gfx_off_ctrl(adev, false); > + for (i = 0; i < info->read_mmr_reg.count; i++) { > if (amdgpu_asic_read_register(adev, se_num, sh_num, > info->read_mmr_reg.dword_offset + i, > ®s[i])) { > DRM_DEBUG_KMS("unallowed offset %#x\n", > info->read_mmr_reg.dword_offset + i); > kfree(regs); > + amdgpu_gfx_off_ctrl(adev, true); > return -EFAULT; > } > + } > + amdgpu_gfx_off_ctrl(adev, true); > n = copy_to_user(out, regs, min(size, alloc_size)); > kfree(regs); > return n ? -EFAULT : 0; > -- > 2.23.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
