[PATCH 1/2] drm/amdgpu: enable mmhub power pate for renoir

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From: changzhu <Changfeng.Zhu@xxxxxxx>

mmhub power gate structure is changed in renoir compared with raven. It
goes through smu_dpm_set_power_gate other than
adev->powerplay.pp_funcs->set_powergating_by_smu in renoir.

So we can realize mmhub power gate in
smu_dpm_set_power_gate ->
smu_powergate_mmhub ->
powergate_mmhub ->
smu_v12_0_powergate_mmhub

Change-Id: I3e1b5ab96f7824abb82b16232dba0a263caeaaa8
Signed-off-by: changzhu <Changfeng.Zhu@xxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c        | 10 ++++++----
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c          |  1 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c        |  3 +--
 drivers/gpu/drm/amd/amdgpu/soc15.c             |  3 ++-
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     |  3 +++
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  1 +
 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h  |  2 ++
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c     |  1 +
 drivers/gpu/drm/amd/powerplay/smu_internal.h   |  2 ++
 drivers/gpu/drm/amd/powerplay/smu_v12_0.c      |  6 ++++++
 10 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index 28d32725285b..3c20668b8d41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -954,15 +954,17 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
 	case AMD_IP_BLOCK_TYPE_VCN:
 	case AMD_IP_BLOCK_TYPE_VCE:
 	case AMD_IP_BLOCK_TYPE_SDMA:
+	case AMD_IP_BLOCK_TYPE_GMC:
 		if (swsmu)
 			ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);
 		else
-			ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
-				(adev)->powerplay.pp_handle, block_type, gate));
+			if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu)
+				ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
+					(adev)->powerplay.pp_handle, block_type, gate));
 		break;
-	case AMD_IP_BLOCK_TYPE_GMC:
 	case AMD_IP_BLOCK_TYPE_ACP:
-		ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
+		if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu)
+			ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
 				(adev)->powerplay.pp_handle, block_type, gate));
 		break;
 	default:
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 46741b3047c5..e8e1e6e86e77 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1202,6 +1202,7 @@ static int gmc_v9_0_hw_init(void *handle)
 
 	switch (adev->asic_type) {
 	case CHIP_RAVEN:
+	case CHIP_RENOIR:
 		/* TODO for renoir */
 		mmhub_v1_0_update_power_gating(adev, true);
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 6965e1e6fa9e..2c15c5e92c38 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -301,8 +301,7 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
 		return;
 
 	if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
-		if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu)
-			amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
 
 	}
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 34e0b4278710..6e132f368130 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1234,7 +1234,8 @@ static int soc15_common_early_init(void *handle)
 				 AMD_CG_SUPPORT_DF_MGCG;
 		adev->pg_flags = AMD_PG_SUPPORT_SDMA |
 				 AMD_PG_SUPPORT_VCN |
-				 AMD_PG_SUPPORT_VCN_DPG;
+				 AMD_PG_SUPPORT_VCN_DPG |
+				 AMD_PG_SUPPORT_MMHUB;
 		adev->external_rev_id = adev->rev_id + 0x91;
 		break;
 	default:
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c21fe7ac5df8..030fbe19b7a3 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -415,6 +415,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 	case AMD_IP_BLOCK_TYPE_SDMA:
 		ret = smu_powergate_sdma(smu, gate);
 		break;
+	case AMD_IP_BLOCK_TYPE_GMC:
+		ret = smu_powergate_mmhub(smu);
+		break;
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8120e7587585..48ea706821fd 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -537,6 +537,7 @@ struct pptable_funcs {
 	int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
 	int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
 	int (*gfx_off_control)(struct smu_context *smu, bool enable);
+	int (*powergate_mmhub)(struct smu_context *smu);
 	int (*register_irq_handler)(struct smu_context *smu);
 	int (*set_azalia_d3_pme)(struct smu_context *smu);
 	int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 9b9f5df0911c..737a3158398c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -66,6 +66,8 @@ int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
 
 int smu_v12_0_init_smc_tables(struct smu_context *smu);
 
+int smu_v12_0_powergate_mmhub(struct smu_context *smu);
+
 int smu_v12_0_fini_smc_tables(struct smu_context *smu);
 
 int smu_v12_0_populate_smc_tables(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 04daf7e9fe05..677759bca955 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -702,6 +702,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
 	.read_smc_arg = smu_v12_0_read_arg,
 	.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
 	.gfx_off_control = smu_v12_0_gfx_off_control,
+	.powergate_mmhub = smu_v12_0_powergate_mmhub,
 	.init_smc_tables = smu_v12_0_init_smc_tables,
 	.fini_smc_tables = smu_v12_0_fini_smc_tables,
 	.populate_smc_tables = smu_v12_0_populate_smc_tables,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 8bcda7871309..b0676ffa8bac 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -65,6 +65,8 @@
 	((smu)->ppt_funcs->notify_memory_pool_location ? (smu)->ppt_funcs->notify_memory_pool_location((smu)) : 0)
 #define smu_gfx_off_control(smu, enable) \
 	((smu)->ppt_funcs->gfx_off_control ? (smu)->ppt_funcs->gfx_off_control((smu), (enable)) : 0)
+#define smu_powergate_mmhub(smu) \
+	((smu)->ppt_funcs->powergate_mmhub ? (smu)->ppt_funcs->powergate_mmhub((smu)) : 0)
 
 #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
 	((smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 139dd737eaa5..3c6286f9e2f3 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -28,6 +28,7 @@
 #include "atomfirmware.h"
 #include "amdgpu_atomfirmware.h"
 #include "smu_v12_0.h"
+#include "smu_v12_0_ppsmc.h"
 #include "soc15_common.h"
 #include "atom.h"
 
@@ -261,6 +262,11 @@ int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
 	return ret;
 }
 
+int smu_v12_0_powergate_mmhub(struct smu_context *smu)
+{
+	return smu_send_smc_msg(smu, PPSMC_MSG_PowerGateMmHub);
+}
+
 int smu_v12_0_init_smc_tables(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-- 
2.17.1

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