On 2019-11-05 5:03 p.m., Huang, JinHuiEric wrote:
> Using unified VBIOS has performance drop in sriov environment.
> The fix is switching to another register instead.
>
> Signed-off-by: Eric Huang <JinhuiEric.Huang@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 829d623..6770bd1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3885,9 +3885,21 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> uint64_t clock;
>
> mutex_lock(&adev->gfx.gpu_clock_mutex);
> - WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
> - clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
> - ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
> + if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
> + uint32_t tmp, lsb, msb, i = 0;
> + do {
> + tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
> + lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);
> + msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
> + i++;
> + udelay(1);
This udelay should be conditional. In the likely case that tmp == msb,
you should never have to delay at all. Maybe put the delay at the start
of the loop with a condition:
if (i != 0)
udelay(1);
So that it only applies before the second and later loops.
Regards,
Felix
> + } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
> + clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
> + } else {
> + WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
> + clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
> + ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
> + }
> mutex_unlock(&adev->gfx.gpu_clock_mutex);
> return clock;
> }
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