Thank you Hersen. Please check the updated patch:
From: Liu, Zhan <Zhan.Liu@xxxxxxx>
Sent: Friday, November 1, 2019 9:18 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Kazlauskas, Nicholas <Nicholas.Kazlauskas@xxxxxxx>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Liu, Zhan <Zhan.Liu@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Wentland, Harry <Harry.Wentland@xxxxxxx>; Wu, Hersen <hersenxs.wu@xxxxxxx>; Zuo, Jerry <Jerry.Zuo@xxxxxxx>
Cc: Yeh, Eagle <Eagle.Yeh@xxxxxxx>; Lazare, Jordan <Jordan.Lazare@xxxxxxx>
Subject: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14
From: Zhan liu <zhan.liu@xxxxxxx>
Date: Fri, 1 Nov 2019 21:10:17 -0400
Subject: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14
[Why]
Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is because there is no ENGINE_ID_DIGD in Navi14. Without this patch, many HDMI related issues (e.g. HDMI S3 resume failure, HDMI pink screen on boot) will be observed.
[How]
If eng_id is larger than ENGINE_ID_DIGD, then add eng_id by 1.
Signed-off-by: Zhan liu <zhan.liu@xxxxxxx>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 924c2e303588..cf886483e380 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1152,6 +1152,11 @@ struct stream_encoder *dcn20_stream_encoder_create(
if (!enc1)
return NULL;
+ if (ASIC_REV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
+ if (eng_id >= ENGINE_ID_DIGD)
+ eng_id++;
+ }
+
dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
&stream_enc_regs[eng_id],
&se_shift, &se_mask);
--
2.21.0
> -----Original Message-----
> From: Wu, Hersen <hersenxs.wu@xxxxxxx>
> Sent: 2019/November/01, Friday 9:23 PM
> To: Liu, Zhan <Zhan.Liu@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx;
> Kazlauskas, Nicholas <Nicholas.Kazlauskas@xxxxxxx>; Lakha, Bhawanpreet
> <Bhawanpreet.Lakha@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>;
> Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>; Wentland, Harry
> <Harry.Wentland@xxxxxxx>; Zuo, Jerry <Jerry.Zuo@xxxxxxx>
> Cc: Yeh, Eagle <Eagle.Yeh@xxxxxxx>; Lazare, Jordan
> <Jordan.Lazare@xxxxxxx>
> Subject: RE: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition
> check for Navi14
>
> Hi Zhan,
>
> The function is shared by NV10,12,14.
>
> Please add ASIC ID check for the DIG D skip.
>
> Thanks!
> Hersen
>
>
> -----Original Message-----
> From: Liu, Zhan <Zhan.Liu@xxxxxxx>
> Sent: Friday, November 1, 2019 9:18 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Kazlauskas, Nicholas
> <Nicholas.Kazlauskas@xxxxxxx>; Lakha, Bhawanpreet
> <Bhawanpreet.Lakha@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Liu,
> Zhan <Zhan.Liu@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>;
> Wentland, Harry <Harry.Wentland@xxxxxxx>; Wu, Hersen
> <hersenxs.wu@xxxxxxx>; Zuo, Jerry <Jerry.Zuo@xxxxxxx>
> Cc: Yeh, Eagle <Eagle.Yeh@xxxxxxx>; Lazare, Jordan
> <Jordan.Lazare@xxxxxxx>
> Subject: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check
> for Navi14
>
> From: Zhan liu <zhan.liu@xxxxxxx>
> Date: Fri, 1 Nov 2019 21:10:17 -0400
> Subject: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check
> for Navi14
>
> [Why]
> Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is because there is no
> ENGINE_ID_DIGD in Navi14. Without this patch, many HDMI related issues
> (e.g. HDMI S3 resume failure, HDMI pink screen on boot) will be observed.
>
> [How]
> If eng_id is larger than ENGINE_ID_DIGD, then add eng_id by 1.
>
> Signed-off-by: Zhan liu <zhan.liu@xxxxxxx>
> ---
> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index 924c2e303588..cf886483e380 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -1152,6 +1152,9 @@ struct stream_encoder
> *dcn20_stream_encoder_create(
> if (!enc1)
> return NULL;
>
> + if (eng_id >= ENGINE_ID_DIGD)
> + eng_id++;
> +
> dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
> &stream_enc_regs[eng_id],
> &se_shift, &se_mask);
> --
> 2.21.0
>
> _______________________________________________
>
> amd-gfx mailing list
>
> amd-gfx@xxxxxxxxxxxxxxxxxxxxx
>
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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