Send amd-gfx mailing list submissions to
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
To subscribe or unsubscribe via the World Wide Web, visit
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
or, via email, send a message with subject or body 'help' to
amd-gfx-request@xxxxxxxxxxxxxxxxxxxxx
You can reach the person managing the list at
amd-gfx-owner@xxxxxxxxxxxxxxxxxxxxx
When replying, please edit your Subject line so it is more specific
than "Re: Contents of amd-gfx digest..."
Today's Topics:
1. Re: [PATCH v2 14/15] drm/amdgpu: Use mmu_range_notifier
instead of hmm_mirror (Jason Gunthorpe)
2. [PATCH] drm/amdgpu: remove PT BOs when unmapping
(Huang, JinHuiEric)
3. [PATCH] drm/amdgpu/renoir: move gfxoff handling into gfx9
module (Alex Deucher)
4. [PATCH] drm/amdgpu/gmc10: properly set BANK_SELECT and
FRAGMENT_SIZE (Alex Deucher)
5. 21:9 monitor resolution incorrect since 4.14 kernel (Neil Mayhew)
----------------------------------------------------------------------
Message: 1
Date: Tue, 29 Oct 2019 19:25:48 +0000
From: Jason Gunthorpe <jgg@xxxxxxxxxxxx>
To: "Yang, Philip" <Philip.Yang@xxxxxxx>
Cc: "linux-mm@xxxxxxxxx" <linux-mm@xxxxxxxxx>, Jerome Glisse
<jglisse@xxxxxxxxxx>, Ralph Campbell <rcampbell@xxxxxxxxxx>, John
Hubbard <jhubbard@xxxxxxxxxx>, "Kuehling, Felix"
<Felix.Kuehling@xxxxxxx>, Juergen Gross <jgross@xxxxxxxx>, "Zhou,
David(ChunMing)" <David1.Zhou@xxxxxxx>, Mike Marciniszyn
<mike.marciniszyn@xxxxxxxxx>, Stefano Stabellini
<sstabellini@xxxxxxxxxx>, Oleksandr Andrushchenko
<oleksandr_andrushchenko@xxxxxxxx>, "linux-rdma@xxxxxxxxxxxxxxx"
<linux-rdma@xxxxxxxxxxxxxxx>, "nouveau@xxxxxxxxxxxxxxxxxxxxx"
<nouveau@xxxxxxxxxxxxxxxxxxxxx>, Dennis Dalessandro
<dennis.dalessandro@xxxxxxxxx>, "amd-gfx@xxxxxxxxxxxxxxxxxxxxx"
<amd-gfx@xxxxxxxxxxxxxxxxxxxxx>, Christoph Hellwig
<hch@xxxxxxxxxxxxx>, "dri-devel@xxxxxxxxxxxxxxxxxxxxx"
<dri-devel@xxxxxxxxxxxxxxxxxxxxx>, "Deucher, Alexander"
<Alexander.Deucher@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx"
<xen-devel@xxxxxxxxxxxxxxxxxxxx>, Boris Ostrovsky
<boris.ostrovsky@xxxxxxxxxx>, Petr Cvek <petrcvekcz@xxxxxxxxx>,
"Koenig, Christian" <Christian.Koenig@xxxxxxx>, Ben Skeggs
<bskeggs@xxxxxxxxxx>
Subject: Re: [PATCH v2 14/15] drm/amdgpu: Use mmu_range_notifier
instead of hmm_mirror
Message-ID: <20191029192544.GU22766@xxxxxxxxxxxx>
Content-Type: text/plain; charset="us-ascii"
On Tue, Oct 29, 2019 at 07:22:37PM +0000, Yang, Philip wrote:
> Hi Jason,
>
> I did quick test after merging amd-staging-drm-next with the
> mmu_notifier branch, which includes this set changes. The test result
> has different failures, app stuck intermittently, GUI no display etc. I
> am understanding the changes and will try to figure out the cause.
Thanks! I'm not surprised by this given how difficult this patch was
to make. Let me know if I can assist in any way
Please ensure to run with lockdep enabled.. Your symptops sounds sort
of like deadlocking?
Regards,
Jason
------------------------------
Message: 2
Date: Tue, 29 Oct 2019 20:06:41 +0000
From: "Huang, JinHuiEric" <JinHuiEric.Huang@xxxxxxx>
To: "amd-gfx@xxxxxxxxxxxxxxxxxxxxx" <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
Cc: "Huang, JinHuiEric" <JinHuiEric.Huang@xxxxxxx>
Subject: [PATCH] drm/amdgpu: remove PT BOs when unmapping
Message-ID:
<1572379585-1401-1-git-send-email-JinhuiEric.Huang@xxxxxxx>
Content-Type: text/plain; charset="iso-8859-1"
The issue is PT BOs are not freed when unmapping VA,
which causes vram usage accumulated is huge in some
memory stress test, such as kfd big buffer stress test.
Function amdgpu_vm_bo_update_mapping() is called by both
amdgpu_vm_bo_update() and amdgpu_vm_clear_freed(). The
solution is replacing amdgpu_vm_bo_update_mapping() in
amdgpu_vm_clear_freed() with removing PT BOs function
to save vram usage.
Change-Id: Ic24e35bff8ca85265b418a642373f189d972a924
Signed-off-by: Eric Huang <JinhuiEric.Huang@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 56 +++++++++++++++++++++++++++++-----
1 file changed, 48 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 0f4c3b2..8a480c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1930,6 +1930,51 @@ static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
}
/**
+ * amdgpu_vm_remove_ptes - free PT BOs
+ *
+ * @adev: amdgpu device structure
+ * @vm: amdgpu vm structure
+ * @start: start of mapped range
+ * @end: end of mapped entry
+ *
+ * Free the page table level.
+ */
+static int amdgpu_vm_remove_ptes(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm, uint64_t start, uint64_t end)
+{
+ struct amdgpu_vm_pt_cursor cursor;
+ unsigned shift, num_entries;
+
+ amdgpu_vm_pt_start(adev, vm, start, &cursor);
+ while (cursor.level < AMDGPU_VM_PTB) {
+ if (!amdgpu_vm_pt_descendant(adev, &cursor))
+ return -ENOENT;
+ }
+
+ while (cursor.pfn < end) {
+ amdgpu_vm_free_table(cursor.entry);
+ num_entries = amdgpu_vm_num_entries(adev, cursor.level - 1);
+
+ if (cursor.entry != &cursor.parent->entries[num_entries - 1]) {
+ /* Next ptb entry */
+ shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
+ cursor.pfn += 1ULL << shift;
+ cursor.pfn &= ~((1ULL << shift) - 1);
+ cursor.entry++;
+ } else {
+ /* Next ptb entry in next pd0 entry */
+ amdgpu_vm_pt_ancestor(&cursor);
+ shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
+ cursor.pfn += 1ULL << shift;
+ cursor.pfn &= ~((1ULL << shift) - 1);
+ amdgpu_vm_pt_descendant(adev, &cursor);
+ }
+ }
+
+ return 0;
+}
+
+/**
* amdgpu_vm_clear_freed - clear freed BOs in the PT
*
* @adev: amdgpu_device pointer
@@ -1949,7 +1994,6 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
struct dma_fence **fence)
{
struct amdgpu_bo_va_mapping *mapping;
- uint64_t init_pte_value = 0;
struct dma_fence *f = NULL;
int r;
@@ -1958,13 +2002,10 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
struct amdgpu_bo_va_mapping, list);
list_del(&mapping->list);
- if (vm->pte_support_ats &&
- mapping->start < AMDGPU_GMC_HOLE_START)
- init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
+ r = amdgpu_vm_remove_ptes(adev, vm,
+ (mapping->start + 0x1ff) & (~0x1ffll),
+ (mapping->last + 1) & (~0x1ffll));
- r = amdgpu_vm_bo_update_mapping(adev, vm, false, NULL,
- mapping->start, mapping->last,
- init_pte_value, 0, NULL, &f);
amdgpu_vm_free_mapping(adev, vm, mapping, f);
if (r) {
dma_fence_put(f);
@@ -1980,7 +2021,6 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
}
return 0;
-
}
/**
--
2.7.4
------------------------------
Message: 3
Date: Tue, 29 Oct 2019 16:10:31 -0400
From: Alex Deucher <alexdeucher@xxxxxxxxx>
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Alex Deucher <alexander.deucher@xxxxxxx>
Subject: [PATCH] drm/amdgpu/renoir: move gfxoff handling into gfx9
module
Message-ID: <20191029201031.1514210-1-alexander.deucher@xxxxxxx>
To properly handle the option parsing ordering.
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++++++
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 -----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9fe95e7693d5..b2b3eb75c48c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1051,6 +1051,12 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
!adev->gfx.rlc.is_rlc_v2_1))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+ AMD_PG_SUPPORT_CP |
+ AMD_PG_SUPPORT_RLC_SMU_HS;
+ break;
+ case CHIP_RENOIR:
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_CP |
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 16c5bb75889f..25e69ea74a41 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1263,11 +1263,6 @@ static int soc15_common_early_init(void *handle)
AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG;
adev->external_rev_id = adev->rev_id + 0x91;
-
- if (adev->pm.pp_feature & PP_GFXOFF_MASK)
- adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
- AMD_PG_SUPPORT_CP |
- AMD_PG_SUPPORT_RLC_SMU_HS;
break;
default:
/* FIXME: not supported yet */
--
2.23.0
------------------------------
Message: 4
Date: Tue, 29 Oct 2019 17:15:44 -0400
From: Alex Deucher <alexdeucher@xxxxxxxxx>
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Alex Deucher <alexander.deucher@xxxxxxx>
Subject: [PATCH] drm/amdgpu/gmc10: properly set BANK_SELECT and
FRAGMENT_SIZE
Message-ID: <20191029211544.1534432-1-alexander.deucher@xxxxxxx>
These were not aligned for optimal performance for GPUVM.
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 9 +++++++++
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 9 +++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index b601c6740ef5..b4f32d853ca1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -155,6 +155,15 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
tmp = mmGCVM_L2_CNTL3_DEFAULT;
+ if (adev->gmc.translate_further) {
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+ } else {
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
+ tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+ }
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
tmp = mmGCVM_L2_CNTL4_DEFAULT;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 2eea702de8ee..945533634711 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -142,6 +142,15 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
tmp = mmMMVM_L2_CNTL3_DEFAULT;
+ if (adev->gmc.translate_further) {
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+ } else {
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
+ tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+ L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+ }
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
tmp = mmMMVM_L2_CNTL4_DEFAULT;
--
2.23.0
------------------------------
Message: 5
Date: Tue, 29 Oct 2019 16:01:29 -0600
From: Neil Mayhew <neil_mayhew@xxxxxxxxxxxxxxxxxxxxx>
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Subject: 21:9 monitor resolution incorrect since 4.14 kernel
Message-ID:
<32e595a2-fdc1-7b13-2e33-c2b8752c60f2@xxxxxxxxxxxxxxxxxxxxx>
Content-Type: text/plain; charset="utf-8"
I have a 21:9 ultrawide monitor connected to an RX 570 with the amdgpu
driver. I'm still using the 4.14 kernel since with later kernels I can't
get the driver to allow use of the full resolution of 2560x1080 and I'm
limited to regular HD, ie 1920x1080. The latest kernel I've tried is
5.4-rc2. My distro is NixOS unstable-small. I have two other monitors
(16:9 and 16:10) connected to the same graphics card.
Is there anything I can do to work around this or try to fix it? I had a
look at the driver sources but couldn't find where the mode is set. I'm
happy to try things if someone can point me in the right direction, even
if it's just to gather better info for a bug report. Using such an old
kernel is becoming really inconvenient.
Some additional info about the situation on 4.14 that may or may not help:
1. The resolution is limited with Wayland but not with X11
2. When the system boots up the resolution is square and the image is
squished horizontally with many columns dropped, both during the boot
process and at the gdm login screen. It's not until after I log with X11
that the resolution is set correctly.
3. The output of xrandr --props is below.
TIA for any help.
--Neil
Screen 0: minimum 320 x 200, current 6160 x 1080, maximum 16384 x 16384
DP-1 connected primary 2560x1080+1920+0 (normal left inverted right x
axis y axis) 798mm x 334mm
_MUTTER_PRESENTATION_OUTPUT: 0
EDID:
00ffffffffffff001e6df9765de80500
091c010380502278eaca95a6554ea126
0f5054256b807140818081c0a9c0b300
d1c08100d1cfcd4600a0a0381f403020
3a001e4e3100001a003a801871382d40
582c4500132a2100001e000000fd0038
4b1e5a18000a202020202020000000fc
004c4720554c545241574944450a01b5
02031af12309070747100403011f1312
8301000065030c0010008c0ad08a20e0
2d10103e96001e4e31000018295900a0
a038274030203a001e4e3100001a0000
00000000000000000000000000000000
00000000000000000000000000000000
0000000000ff003830394e544b464244
3136350a0000000000000000000000a4
dither: off
supported: off, on
audio: auto
supported: off, on, auto
scaling mode: None
supported: None, Full, Center, Full aspect
underscan vborder: 0
range: (0, 128)
underscan hborder: 0
range: (0, 128)
underscan: off
supported: off, on, auto
coherent: 1
range: (0, 1)
link-status: Good
supported: Good, Bad
CONNECTOR_ID: 48
supported: 48
non-desktop: 0
supported: 0, 1
2560x1080 59.98 + 74.99*
1920x1080 74.99 59.96 50.00 59.99 59.94 59.93
1680x1050 59.95 59.88
[etc.]
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20191029/471e1fcb/attachment.html>
------------------------------
Subject: Digest Footer
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
------------------------------
End of amd-gfx Digest, Vol 41, Issue 390
****************************************
