Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Le Ma Sent: Monday, October 28, 2019 7:31 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Ma, Le <Le.Ma@xxxxxxx> Subject: [PATCH 4/4] drm/amdgpu: remove ras global recovery handling from ras_controller_int handler From: Le Ma <Le.Ma@xxxxxxx> Change-Id: Ia8a61a4b3bd529f0f691e43e69b299d7d151c0c2 Signed-off-by: Le Ma <Le.Ma@xxxxxxx> --- drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c index 0db458f..876690a 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c @@ -324,7 +324,11 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device RAS_CNTLR_INTERRUPT_CLEAR, 1); WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); - amdgpu_ras_global_ras_isr(adev); + /* + * ras_controller_int is dedicated for nbif ras error, + * not the global interrupt for sync flood + */ + amdgpu_ras_reset_gpu(adev, true); [Guchun]We need to add one printing here to tell audience, who and why resets gpu? And moreover, in the removed global ras isr handler amdgpu_ras_global_ras_isr, we call amdgpu_ras_reset_gpu with is_baco parameter "false", but now we use "true" here? } } -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
