The value of the register mmMP1_SMN_C2PMSG_90 should be 0 when initializing smu and after resuming smu. Signed-off-by: chen gong <curry.gong@xxxxxxx> --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 ++- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 15 ++++++++++----- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 3ce01e1..d93040b 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -738,6 +738,7 @@ static int smu_early_init(void *handle) smu->adev = adev; smu->pm_enabled = !!amdgpu_dpm; smu->is_apu = false; + smu->not_yet_sent_one_msg = true; mutex_init(&smu->mutex); return smu_set_funcs(adev); @@ -1381,7 +1382,7 @@ static int smu_resume(void *handle) smu_set_gfx_cgpg(&adev->smu, true); smu->disable_uclk_switch = 0; - + smu->not_yet_sent_one_msg = true; pr_info("SMU is resumed successfully!\n"); return 0; diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index 8120e75..1c03163 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -388,6 +388,7 @@ struct smu_context uint32_t default_power_profile_mode; bool pm_enabled; bool is_apu; + bool not_yet_sent_one_msg; uint32_t smc_if_version; diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c index 139dd73..2199a39 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c @@ -113,10 +113,11 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg, if (index < 0) return index; - ret = smu_v12_0_wait_for_response(smu); - if (ret) - pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n", - index, ret, param); + if(!smu->not_yet_sent_one_msg){ + ret = smu_v12_0_wait_for_response(smu); + if (ret) + pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",index, ret, param); + } WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); @@ -125,9 +126,13 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg, smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index); ret = smu_v12_0_wait_for_response(smu); - if (ret) + if (ret){ pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n", index, ret, param); + } + else if(smu->not_yet_sent_one_msg){ + smu->not_yet_sent_one_msg = false; + } return ret; } -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx