> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> Marek Olšák
> Sent: Tuesday, October 22, 2019 5:23 PM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH] drm/amdgpu: Allow reading more status registers on si/cik
>
> From: Marek Olšák <marek.olsak@xxxxxxx>
>
> Allow userspace to read the same status registers for every family.
> Based on commit c7890fea, added any of these registers if defined in the
> include files of each architecture.
>
> Signed-off-by: Marek Olšák <marek.olsak@xxxxxxx>
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/cik.c | 19 +++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
> drivers/gpu/drm/amd/amdgpu/si.c | 11 +++++++++++
> drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
> 5 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index a787d838974e..08610081bd9e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -76,23 +76,24 @@
> * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
> * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
> * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
> * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
> * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
> * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
> * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
> * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
> * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
> * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
> + * - 3.36.0 - Allow reading more status registers on si/cik
> */
> #define KMS_DRIVER_MAJOR 3
> -#define KMS_DRIVER_MINOR 35
> +#define KMS_DRIVER_MINOR 36
> #define KMS_DRIVER_PATCHLEVEL 0
>
> int amdgpu_vram_limit = 0;
> int amdgpu_vis_vram_limit = 0;
> int amdgpu_gart_size = -1; /* auto */
> int amdgpu_gtt_size = -1; /* auto */
> int amdgpu_moverate = -1; /* auto */
> int amdgpu_benchmarking = 0;
> int amdgpu_testing = 0;
> int amdgpu_audio = -1;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
> b/drivers/gpu/drm/amd/amdgpu/cik.c
> index fc8b34480f66..2d64d270725d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -959,20 +959,39 @@ static bool cik_read_bios_from_rom(struct
> amdgpu_device *adev,
> WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
> for (i = 0; i < length_dw; i++)
> dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
> spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
>
> return true;
> }
>
> static const struct amdgpu_allowed_register_entry
> cik_allowed_read_registers[] = {
> {mmGRBM_STATUS},
> + {mmGRBM_STATUS2},
> + {mmGRBM_STATUS_SE0},
> + {mmGRBM_STATUS_SE1},
> + {mmGRBM_STATUS_SE2},
> + {mmGRBM_STATUS_SE3},
> + {mmSRBM_STATUS},
> + {mmSRBM_STATUS2},
> + {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
> + {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
> + {mmCP_STAT},
> + {mmCP_STALLED_STAT1},
> + {mmCP_STALLED_STAT2},
> + {mmCP_STALLED_STAT3},
> + {mmCP_CPF_BUSY_STAT},
> + {mmCP_CPF_STALLED_STAT1},
> + {mmCP_CPF_STATUS},
> + {mmCP_CPC_BUSY_STAT},
> + {mmCP_CPC_STALLED_STAT1},
> + {mmCP_CPC_STATUS},
> {mmGB_ADDR_CONFIG},
> {mmMC_ARB_RAMCFG},
> {mmGB_TILE_MODE0},
> {mmGB_TILE_MODE1},
> {mmGB_TILE_MODE2},
> {mmGB_TILE_MODE3},
> {mmGB_TILE_MODE4},
> {mmGB_TILE_MODE5},
> {mmGB_TILE_MODE6},
> {mmGB_TILE_MODE7},
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
> b/drivers/gpu/drm/amd/amdgpu/nv.c index 46206a1a1f4d..22ab1955b923
> 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -171,20 +171,21 @@ static struct soc15_allowed_register_entry
> nv_allowed_read_registers[] = {
> { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
> { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, #endif
> { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
> + { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
> { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, };
>
> static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32
> se_num,
> u32 sh_num, u32 reg_offset)
> {
> uint32_t val;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c
> b/drivers/gpu/drm/amd/amdgpu/si.c index 493af42152f2..29024e64c886
> 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -968,20 +968,31 @@ static void si_smc_wreg(struct amdgpu_device
> *adev, u32 reg, u32 v)
> unsigned long flags;
>
> spin_lock_irqsave(&adev->smc_idx_lock, flags);
> WREG32(SMC_IND_INDEX_0, (reg));
> WREG32(SMC_IND_DATA_0, (v));
> spin_unlock_irqrestore(&adev->smc_idx_lock, flags); }
>
> static struct amdgpu_allowed_register_entry si_allowed_read_registers[] =
> {
> {GRBM_STATUS},
> + {mmGRBM_STATUS2},
> + {mmGRBM_STATUS_SE0},
> + {mmGRBM_STATUS_SE1},
> + {mmSRBM_STATUS},
> + {mmSRBM_STATUS2},
> + {DMA_STATUS_REG + DMA0_REGISTER_OFFSET},
> + {DMA_STATUS_REG + DMA1_REGISTER_OFFSET},
> + {mmCP_STAT},
> + {mmCP_STALLED_STAT1},
> + {mmCP_STALLED_STAT2},
> + {mmCP_STALLED_STAT3},
> {GB_ADDR_CONFIG},
> {MC_ARB_RAMCFG},
> {GB_TILE_MODE0},
> {GB_TILE_MODE1},
> {GB_TILE_MODE2},
> {GB_TILE_MODE3},
> {GB_TILE_MODE4},
> {GB_TILE_MODE5},
> {GB_TILE_MODE6},
> {GB_TILE_MODE7},
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 9be0168217f5..741b564b4aa5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -332,20 +332,21 @@ static struct soc15_allowed_register_entry
> soc15_allowed_read_registers[] = {
> { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
> { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
> { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
> + { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
> { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
> { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
> { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, };
>
> static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev,
> u32 se_num,
> u32 sh_num, u32 reg_offset)
> {
> uint32_t val;
> --
> 2.17.1
>
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