Reviewed-by: Evan Quan <evan.quan@xxxxxxx>
> -----Original Message-----
> From: Kim, Jonathan <Jonathan.Kim@xxxxxxx>
> Sent: 2019年10月17日 10:06
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Kuehling, Felix <Felix.Kuehling@xxxxxxx>; Quan, Evan
> <Evan.Quan@xxxxxxx>; Kim, Jonathan <Jonathan.Kim@xxxxxxx>; Kim,
> Jonathan <Jonathan.Kim@xxxxxxx>
> Subject: [PATCH] drm/amdgpu: disable c-states on xgmi perfmons
>
> read or writes to df registers when gpu df is in c-states will result in
> hang. df c-states should be disabled prior to read or writes then
> re-enabled after read or writes.
>
> v2: use old powerplay routines for vega20
>
> Change-Id: I6d5a83e4fe13e29c73dfb03a94fe7c611e867fec
> Signed-off-by: Jonathan Kim <Jonathan.Kim@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 36
> +++++++++++++++++++++++++++-
> 1 file changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> index 16fbd2bc8ad1..f403c62c944e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> @@ -93,6 +93,21 @@ const struct attribute_group *df_v3_6_attr_groups[] =
> {
> NULL
> };
>
> +static df_v3_6_set_df_cstate(struct amdgpu_device *adev, int allow)
> +{
> + int r = 0;
> +
> + if (is_support_sw_smu(adev)) {
> + r = smu_set_df_cstate(&adev->smu, allow);
> + } else if (adev->powerplay.pp_funcs
> + && adev->powerplay.pp_funcs->set_df_cstate) {
> + r = adev->powerplay.pp_funcs->set_df_cstate(
> + adev->powerplay.pp_handle, allow);
> + }
> +
> + return r;
> +}
> +
> static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
> uint32_t ficaa_val)
> {
> @@ -102,6 +117,9 @@ static uint64_t df_v3_6_get_fica(struct
> amdgpu_device *adev,
> address = adev->nbio.funcs->get_pcie_index_offset(adev);
> data = adev->nbio.funcs->get_pcie_data_offset(adev);
>
> + if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
> + return 0xFFFFFFFFFFFFFFFF;
> +
> spin_lock_irqsave(&adev->pcie_idx_lock, flags);
> WREG32(address,
> smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
> WREG32(data, ficaa_val);
> @@ -114,6 +132,8 @@ static uint64_t df_v3_6_get_fica(struct
> amdgpu_device *adev,
>
> spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
>
> + df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
> +
> return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
> }
>
> @@ -125,6 +145,9 @@ static void df_v3_6_set_fica(struct amdgpu_device
> *adev, uint32_t ficaa_val,
> address = adev->nbio.funcs->get_pcie_index_offset(adev);
> data = adev->nbio.funcs->get_pcie_data_offset(adev);
>
> + if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
> + return;
> +
> spin_lock_irqsave(&adev->pcie_idx_lock, flags);
> WREG32(address,
> smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
> WREG32(data, ficaa_val);
> @@ -134,8 +157,9 @@ static void df_v3_6_set_fica(struct amdgpu_device
> *adev, uint32_t ficaa_val,
>
> WREG32(address,
> smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
> WREG32(data, ficadh_val);
> -
> spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
> +
> + df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
> }
>
> /*
> @@ -153,12 +177,17 @@ static void df_v3_6_perfmon_rreg(struct
> amdgpu_device *adev,
> address = adev->nbio.funcs->get_pcie_index_offset(adev);
> data = adev->nbio.funcs->get_pcie_data_offset(adev);
>
> + if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
> + return;
> +
> spin_lock_irqsave(&adev->pcie_idx_lock, flags);
> WREG32(address, lo_addr);
> *lo_val = RREG32(data);
> WREG32(address, hi_addr);
> *hi_val = RREG32(data);
> spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
> +
> + df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
> }
>
> /*
> @@ -175,12 +204,17 @@ static void df_v3_6_perfmon_wreg(struct
> amdgpu_device *adev, uint32_t lo_addr,
> address = adev->nbio.funcs->get_pcie_index_offset(adev);
> data = adev->nbio.funcs->get_pcie_data_offset(adev);
>
> + if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
> + return;
> +
> spin_lock_irqsave(&adev->pcie_idx_lock, flags);
> WREG32(address, lo_addr);
> WREG32(data, lo_val);
> WREG32(address, hi_addr);
> WREG32(data, hi_val);
> spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
> +
> + df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
> }
>
> /* get the number of df counters available */
> --
> 2.17.1
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