Reviewed-by: Jack Xiao <Jack.Xiao@xxxxxxx>
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Kenneth Feng
Sent: Wednesday, October 16, 2019 4:58 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Feng, Kenneth <Kenneth.Feng@xxxxxxx>
Subject: [PATCH] drm/amd/powerplay: bug fix for memory clock request from display
In some cases, display fixes memory clock frequency to a high value rather than the natural memory clock switching.
When we comes back from s3 resume, the request from display is not reset, this causes the bug which makes the memory clock goes into a low value.
Then due to the insuffcient memory clock, the screen flicks.
Signed-off-by: Kenneth Feng <kenneth.feng@xxxxxxx>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e2a03f4..ee374df 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1354,6 +1354,8 @@ static int smu_resume(void *handle)
if (smu->is_apu)
smu_set_gfx_cgpg(&adev->smu, true);
+ smu->disable_uclk_switch = 0;
+
mutex_unlock(&smu->mutex);
pr_info("SMU is resumed successfully!\n");
--
2.7.4
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