Series is Acked-by: Harry Wentland <harry.wentland@xxxxxxx> Harry On 2019-10-09 5:05 p.m., Bhawanpreet Lakha wrote: > Hi all, > > There was a delta betwwen internal dcn21 code and upstream dcn21 code. > These changes bring them inline. > > > Summary of Changes > *Add RN registors > *Add dcn12 hwseq and link_encoder > *RN specific fixes > *aux timeout support > *bounding box changes > > Bhawanpreet Lakha (12): > drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs > drm/amd/display: Add DCN_BASE regs > drm/amd/display: Add renoir hw_seq > drm/amd/display: create dcn21_link_encoder files > drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY programming > drm/amd/display: fix incorrect page table address for renoir > drm/amd/display: add detile buffer size for renoir > drm/amd/display: update dcn21 hubbub registers > drm/amd/display: update renoir bounding box and res_caps > drm/amd/display: change PP_SM defs to 8 > drm/amd/display: handle "18" case in TruncToValidBPP > drm/amd/display: use requested_dispclk_khz instead of clk > > Dmytro Laktyushkin (4): > drm/amd/display: enable hostvm based on roimmu active for dcn2.1 > drm/amd/display: initialize RN gpuvm context programming function > drm/amd/display: correct dcn21 NUM_VMID to 16 > drm/amd/display: update odm mode validation to be in line with policy > > Eric Yang (2): > drm/amd/display: use dcn10 version of program tiling on Renoir > drm/amd/display: add sanity check for clk table from smu > > Lewis Huang (3): > drm/amd/display: move the bounding box patch before calculate wm > drm/amd/display: Temporary workaround to toggle watermark setting > drm/amd/display: enable smu set dcfclk > > Michael Strauss (1): > drm/amd/display: Fix rn audio playback and video playback speed > > Sung Lee (1): > drm/amd/display: add dummy functions to smu for Renoir Silicon Diags > > abdoulaye berthe (2): > drm/amd/display: update register field access mechanism > drm/amd/display: configurable aux timeout support > > joseph gravenor (1): > drm/amd/display: fix header for RN clk mgr > > .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 23 +- > .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 19 +- > .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14 + > drivers/gpu/drm/amd/display/dc/dc.h | 2 + > drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 82 +++- > drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 187 ++++++++- > .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 1 + > .../amd/display/dc/dce100/dce100_resource.c | 15 +- > .../amd/display/dc/dce110/dce110_resource.c | 14 +- > .../amd/display/dc/dce112/dce112_resource.c | 15 +- > .../amd/display/dc/dce120/dce120_resource.c | 15 +- > .../drm/amd/display/dc/dce80/dce80_resource.c | 14 +- > .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 + > .../amd/display/dc/dcn10/dcn10_link_encoder.h | 35 +- > .../drm/amd/display/dc/dcn10/dcn10_resource.c | 15 +- > .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 + > .../amd/display/dc/dcn20/dcn20_link_encoder.h | 7 + > .../drm/amd/display/dc/dcn20/dcn20_resource.c | 31 +- > drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 2 +- > .../drm/amd/display/dc/dcn21/dcn21_hubbub.c | 116 ++++-- > .../drm/amd/display/dc/dcn21/dcn21_hubbub.h | 34 +- > .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 +- > .../drm/amd/display/dc/dcn21/dcn21_hwseq.c | 122 ++++++ > .../drm/amd/display/dc/dcn21/dcn21_hwseq.h | 33 ++ > .../amd/display/dc/dcn21/dcn21_link_encoder.c | 384 ++++++++++++++++++ > .../amd/display/dc/dcn21/dcn21_link_encoder.h | 51 +++ > .../drm/amd/display/dc/dcn21/dcn21_resource.c | 269 ++++++++++-- > drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 +- > .../dc/dml/dcn21/display_mode_vba_21.c | 11 +- > .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h | 3 + > .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 + > .../drm/amd/display/dc/inc/hw/aux_engine.h | 3 + > .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 + > .../gpu/drm/amd/display/dc/inc/hw/mem_input.h | 1 + > .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 + > .../include/asic_reg/dcn/dcn_2_1_0_offset.h | 10 + > .../gpu/drm/amd/include/renoir_ip_offset.h | 34 ++ > 37 files changed, 1461 insertions(+), 125 deletions(-) > create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c > create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h > create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c > create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h > _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
