On 2019-09-25 2:15 p.m., Zhao, Yong wrote:
> This was done on GFX9 previously, now do it for GFX10.
>
> Change-Id: I4442e60534c59bc9526a673559f018ba8058deac
> Signed-off-by: Yong Zhao <Yong.Zhao@xxxxxxx>
Reviewed-by: Felix Kuehling <Felix.Kuehling@xxxxxxx>
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 23 +++----------------
> 1 file changed, 3 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> index fe5b702c75ce..64568ed32793 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> @@ -42,6 +42,7 @@
> #include "v10_structs.h"
> #include "nv.h"
> #include "nvd.h"
> +#include "gfxhub_v2_0.h"
>
> enum hqd_dequeue_request_type {
> NO_ACTION = 0,
> @@ -251,11 +252,6 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
> ATC_VMID0_PASID_MAPPING__VALID_MASK;
>
> pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
> - /*
> - * need to do this twice, once for gfx and once for mmhub
> - * for ATC add 16 to VMID for mmhub, for IH different registers.
> - * ATC_VMID0..15 registers are separate from ATC_VMID16..31.
> - */
>
> pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
> WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
> @@ -910,7 +906,6 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
> uint64_t page_table_base)
> {
> struct amdgpu_device *adev = get_amdgpu_device(kgd);
> - uint64_t base = page_table_base | AMDGPU_PTE_VALID;
>
> if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
> pr_err("trying to set page table base for wrong VMID %u\n",
> @@ -918,18 +913,6 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
> return;
> }
>
> - /* TODO: take advantage of per-process address space size. For
> - * now, all processes share the same address space size, like
> - * on GFX8 and older.
> - */
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0);
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0);
> -
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2),
> - lower_32_bits(adev->vm_manager.max_pfn - 1));
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2),
> - upper_32_bits(adev->vm_manager.max_pfn - 1));
> -
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));
> + /* SDMA is on gfxhub as well on Navi1* series */
> + gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base);
> }
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