Am 26.09.19 um 15:40 schrieb Alex Deucher:
> On Thu, Sep 26, 2019 at 8:29 AM Christian König
> <ckoenig.leichtzumerken@xxxxxxxxx> wrote:
>> Stop, wait a second guys!
>>
>> This will disable the workaround for Navi10 and that is certainly not correct:
>>
>> !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12)
>>
> Actually, I think it's correct. When I merged the baco patch, I
> accidentally dropped the navi checks. E.g.,
> @@ -245,8 +245,9 @@ static void gmc_v10_0_flush_gpu_tlb(struct
> amdgpu_device *adev,
> mutex_lock(&adev->mman.gtt_window_lock);
>
> gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0);
> - if (!adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready ||
> - adev->asic_type != CHIP_NAVI10) {
> + if (!adev->mman.buffer_funcs_enabled ||
> + !adev->ib_pool_ready ||
> + adev->in_gpu_reset) {
> gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0);
> mutex_unlock(&adev->mman.gtt_window_lock);
> return;
> I think it should have been
> adev->asic_type != CHIP_NAVI10 && adev->asic_type != CHIP_NAVI14 &&
> adev->asic_type != CHIP_NAVI12
My last status is that Navi12 is not supposed to need that workaround,
that's why we checked Navi10 and later Navi14 separately.
It's possible that I miss-read the !(adev->asic_type >= CHIP_NAVI10 &&
adev->asic_type <= CHIP_NAVI12) check here, but either way that looks to
complicated to me.
We should rather mention every affected asic type separately here.
Regards,
Christian.
>
> Alex
>
>> Christian.
>>
>>
>> Am 26.09.19 um 14:26 schrieb Deucher, Alexander:
>>
>> Please add a patch description. With that fixed:
>> Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
>> ________________________________
>> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Yuan, Xiaojie <Xiaojie.Yuan@xxxxxxx>
>> Sent: Thursday, September 26, 2019 4:09 AM
>> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
>> Cc: alexdeucher@xxxxxxxxx <alexdeucher@xxxxxxxxx>
>> Subject: Re: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' workaround for navi
>>
>> Hi Alex,
>>
>> This patch is to add the asic_type check which is missing after drm-next branch rebase.
>>
>> BR,
>> Xiaojie
>> ________________________________
>> From: Yuan, Xiaojie <Xiaojie.Yuan@xxxxxxx>
>> Sent: Thursday, September 26, 2019 4:08 PM
>> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
>> Cc: alexdeucher@xxxxxxxxx <alexdeucher@xxxxxxxxx>; Yuan, Xiaojie <Xiaojie.Yuan@xxxxxxx>
>> Subject: [PATCH] drm/amdgpu/gmc10: apply the 'invalidation from sdma' workaround for navi
>>
>> Fixes: 767acabdac81 ("drm/amd/powerplay: add baco smu reset function for smu11")
>> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@xxxxxxx>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> index cb3f61873baa..dc2e68e019eb 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> @@ -292,6 +292,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
>>
>> if (!adev->mman.buffer_funcs_enabled ||
>> !adev->ib_pool_ready ||
>> + !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12) ||
>> adev->in_gpu_reset) {
>> gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
>> mutex_unlock(&adev->mman.gtt_window_lock);
>> --
>> 2.20.1
>>
>>
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>> amd-gfx@xxxxxxxxxxxxxxxxxxxxx
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>>
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