> -----Original Message-----
> From: Hawking Zhang <Hawking.Zhang@xxxxxxx>
> Sent: 2019年8月28日 21:03
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Zhou1, Tao <Tao.Zhou1@xxxxxxx>;
> Deucher, Alexander <Alexander.Deucher@xxxxxxx>
> Cc: Zhang, Hawking <Hawking.Zhang@xxxxxxx>
> Subject: [PATCH 6/7] drm/amdgpu: add ras_late_init callback function for
> nbio v7_4
>
> ras_late_init callback function will be used to do common ras init in late init
> phase.
>
> Signed-off-by: Hawking Zhang <Hawking.Zhang@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
> drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 41
> ++++++++++++++++++++++++++++++++
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
> index a04c5ea..51078da6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
> @@ -81,12 +81,14 @@ struct amdgpu_nbio_funcs {
> void (*handle_ras_err_event_athub_intr_no_bifring)(struct
> amdgpu_device *adev);
> int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
> int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device
> *adev);
> + int (*ras_late_init)(struct amdgpu_device *adev);
> };
>
> struct amdgpu_nbio {
> const struct nbio_hdp_flush_reg *hdp_flush_reg;
> struct amdgpu_irq_src ras_controller_irq;
> struct amdgpu_irq_src ras_err_event_athub_irq;
> + struct ras_common_if *ras_if;
> const struct amdgpu_nbio_funcs *funcs; };
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index faf9300..367f9d6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -23,6 +23,7 @@
> #include "amdgpu.h"
> #include "amdgpu_atombios.h"
> #include "nbio_v7_4.h"
> +#include "amdgpu_ras.h"
>
> #include "nbio/nbio_7_4_offset.h"
> #include "nbio/nbio_7_4_sh_mask.h"
> @@ -468,6 +469,45 @@ static int
> nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a
> return 0;
> }
>
> +static int nbio_v7_4_ras_late_init(struct amdgpu_device *adev) {
> + int r;
> + struct ras_ih_if ih_info;
> + struct ras_fs_if fs_info = {
> + .sysfs_name = "nbio_err_count",
> + .debugfs_name = "nbio_err_inject",
[Tao] The ras block name is AMDGPU_RAS_BLOCK_PCIE_BIF and its string name is pcie_bif in ras_block_string,
QA may be confused in the future.
> + };
> +
> + if (!adev->nbio.ras_if) {
> + adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if),
> GFP_KERNEL);
> + if (!adev->nbio.ras_if)
> + return -ENOMEM;
> + adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
> + adev->nbio.ras_if->type =
> AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
> + adev->nbio.ras_if->sub_block_index = 0;
> + strcpy(adev->nbio.ras_if->name, "nbio");
> + }
> + ih_info.head = fs_info.head = *adev->nbio.ras_if;
> + r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
> + &fs_info, &ih_info);
> + if (r)
> + goto free;
> +
> + if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
> + r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
> + if (r)
> + goto free;
> + r = amdgpu_irq_get(adev, &adev-
> >nbio.ras_err_event_athub_irq, 0);
> + if (r)
> + goto free;
> + }
> +
> + return 0;
> +free:
> + kfree(adev->nbio.ras_if);
> + return r;
> +}
> +
> const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
> .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
> .get_hdp_flush_done_offset =
> nbio_v7_4_get_hdp_flush_done_offset,
> @@ -493,4 +533,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
> .handle_ras_err_event_athub_intr_no_bifring =
> nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
> .init_ras_controller_interrupt =
> nbio_v7_4_init_ras_controller_interrupt,
> .init_ras_err_event_athub_interrupt =
> nbio_v7_4_init_ras_err_event_athub_interrupt,
> + .ras_late_init = nbio_v7_4_ras_late_init,
> };
> --
> 2.7.4
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