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This was an old patch I accidentally sent out. Please ignore.
Alex
From: Christian König <ckoenig.leichtzumerken@xxxxxxxxx>
Sent: Thursday, August 22, 2019 5:32 AM To: Alex Deucher <alexdeucher@xxxxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx> Subject: Re: [PATCH 2/2] drm/radeon: use WAIT_REG_MEM special op for CP HDP flush Every time we actually tried this it just ended in users reporting CP hangs.
Christian. Am 22.08.19 um 00:20 schrieb Alex Deucher: > Flush via the ring works differently on CIK and requires a > special sequence. > > Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > drivers/gpu/drm/radeon/cik.c | 73 +++++++++++++++++++++++++++----------------- > 1 file changed, 45 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index 0847367..03dd075 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -3485,6 +3485,48 @@ int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) > return r; > } > > +static void cik_gfx_hdp_flush(struct radeon_device *rdev, > + int ridx) > +{ > + struct radeon_ring *ring = &rdev->ring[ridx]; > + u32 ref_and_mask; > + > + switch (ring->idx) { > + case CAYMAN_RING_TYPE_CP1_INDEX: > + case CAYMAN_RING_TYPE_CP2_INDEX: > + switch (ring->me) { > + case 0: > + ref_and_mask = CP2 << ring->pipe; > + break; > + case 1: > + ref_and_mask = CP6 << ring->pipe; > + break; > + default: > + return; > + } > + break; > + case RADEON_RING_TYPE_GFX_INDEX: > + ref_and_mask = CP0; > + break; > + default: > + return; > + } > + > + radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); > + radeon_ring_write(ring, ((CP_WAIT_REG_MEM_TIMEOUT - > + PACKET3_SET_UCONFIG_REG_START) >> 2)); > + radeon_ring_write(ring, 0xfff); > + > + radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); > + radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* special op */ > + WAIT_REG_MEM_FUNCTION(3))); /* == */ > + radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2); > + radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2); > + radeon_ring_write(ring, ref_and_mask); > + radeon_ring_write(ring, ref_and_mask); > + radeon_ring_write(ring, 0xa); /* poll interval */ > +} > + > /** > * cik_fence_gfx_ring_emit - emit a fence on the gfx ring > * > @@ -3511,15 +3553,7 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, > radeon_ring_write(ring, fence->seq); > radeon_ring_write(ring, 0); > /* HDP flush */ > - /* We should be using the new WAIT_REG_MEM special op packet here > - * but it causes the CP to hang > - */ > - radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); > - radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | > - WRITE_DATA_DST_SEL(0))); > - radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); > - radeon_ring_write(ring, 0); > - radeon_ring_write(ring, 0); > + cik_gfx_hdp_flush(rdev, fence->ring); > } > > /** > @@ -3549,15 +3583,7 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev, > radeon_ring_write(ring, fence->seq); > radeon_ring_write(ring, 0); > /* HDP flush */ > - /* We should be using the new WAIT_REG_MEM special op packet here > - * but it causes the CP to hang > - */ > - radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); > - radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | > - WRITE_DATA_DST_SEL(0))); > - radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); > - radeon_ring_write(ring, 0); > - radeon_ring_write(ring, 0); > + cik_gfx_hdp_flush(rdev, fence->ring); > } > > bool cik_semaphore_ring_emit(struct radeon_device *rdev, > @@ -5369,16 +5395,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) > radeon_ring_write(ring, VMID(0)); > > /* HDP flush */ > - /* We should be using the WAIT_REG_MEM packet here like in > - * cik_fence_ring_emit(), but it causes the CP to hang in this > - * context... > - */ > - radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); > - radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | > - WRITE_DATA_DST_SEL(0))); > - radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); > - radeon_ring_write(ring, 0); > - radeon_ring_write(ring, 0); > + cik_gfx_hdp_flush(rdev, ridx); > > /* bits 0-15 are the VM contexts0-15 */ > radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
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