From: tiancyin <tianci.yin@xxxxxxx> update the smu11_driver_if_navi10.h since navi14 smu fw update to 53.12 Change-Id: If0f729ec87c98f24e1794f0847eac5ba23671e34 Reviewed-by: Evan Quan <evan.quan@xxxxxxx> Signed-off-by: tiancyin <tianci.yin@xxxxxxx> --- .../drm/amd/powerplay/inc/smu11_driver_if_navi10.h | 25 +++++++++++++++++----- drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h index 6d9e79e..ac0120e 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h @@ -506,10 +506,11 @@ typedef struct { uint32_t Status; uint16_t DieTemperature; - uint16_t MemoryTemperature; + uint16_t CurrentMemoryTemperature; - uint16_t SelectedCardPower; - uint16_t Reserved4; + uint16_t MemoryTemperature; + uint8_t MemoryHotspotPosition; + uint8_t Reserved4; uint32_t BoardLevelEnergyAccumulator; } OutOfBandMonitor_t; @@ -801,7 +802,12 @@ typedef struct { // Mvdd Svi2 Div Ratio Setting uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) - uint32_t BoardReserved[9]; + uint8_t RenesesLoadLineEnabled; + uint8_t GfxLoadlineResistance; + uint8_t SocLoadlineResistance; + uint8_t Padding8_Loadline; + + uint32_t BoardReserved[8]; // Padding for MMHUB - do not modify this uint32_t MmHubPadding[8]; // SMU internal use @@ -905,13 +911,22 @@ typedef struct { } Watermarks_t; typedef struct { + uint16_t avgPsmCount[28]; + uint16_t minPsmCount[28]; + float avgPsmVoltage[28]; + float minPsmVoltage[28]; + + uint32_t MmHubPadding[32]; // SMU internal use +} AvfsDebugTable_t_NV14; + +typedef struct { uint16_t avgPsmCount[36]; uint16_t minPsmCount[36]; float avgPsmVoltage[36]; float minPsmVoltage[36]; uint32_t MmHubPadding[8]; // SMU internal use -} AvfsDebugTable_t; +} AvfsDebugTable_t_NV10; typedef struct { uint8_t AvfsVersion; diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h index 97605e9..ee8542d 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h @@ -28,7 +28,7 @@ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF #define SMU11_DRIVER_IF_VERSION_VG20 0x13 #define SMU11_DRIVER_IF_VERSION_NV10 0x33 -#define SMU11_DRIVER_IF_VERSION_NV14 0x33 +#define SMU11_DRIVER_IF_VERSION_NV14 0x34 /* MP Apertures */ #define MP0_Public 0x03800000 -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx