This series enables additional RAS features for vega20. Dennis Li (6): drm/amd/include: add bitfield define for EDC registers drm/amd/include: add define of TCP_EDC_CNT_NEW drm/amdgpu: add define for gfx ras subblock drm/amdgpu: add RAS callback for gfx drm/amdgpu: support gfx ras error injection and err_cnt query drm/amdgpu: disable inject for failed subblocks of gfx Hawking Zhang (8): drm/amdgpu: move some ras data structure to amdgpu_ras.h drm/amdgpu: init RSMU and UMC ip base address for vega20 drm/amdgpu: add amdgpu_umc_functions structure drm/amdgpu: add rsmu v_0_0_2 ip headers drm/amdgpu: add umc v6_1_1 IP headers drm/amdgpu: add umc v6_1 query error count support drm/amdgpu: init umc v6_1 functions for vega20 drm/amdgpu: querry umc error count Tao Zhou (12): drm/amdgpu: add ras error count after each query (v2) drm/amdgpu: add RREG64/WREG64(_PCIE) operations drm/amdgpu: use 64bit operation macros for umc drm/amdgpu: switch to amdgpu_umc structure drm/amdgpu: update algorithm of umc uncorrectable error counting drm/amdgpu: add support for recording ras error address drm/amdgpu: add structures for umc error address translation drm/amdgpu: query umc ras error address drm/amdgpu: allow ras interrupt callback to return error data drm/amdgpu: update interrupt callback for all ras clients drm/amdgpu: add check for ras error type drm/amdgpu: remove ras_reserve_vram in ras injection drivers/gpu/drm/amd/amdgpu/Makefile | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 17 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 145 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 308 ++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 37 + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 784 +++++++++++++++++- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 19 + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 + drivers/gpu/drm/amd/amdgpu/soc15.c | 45 + drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 243 ++++++ drivers/gpu/drm/amd/amdgpu/umc_v6_1.h | 39 + drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 2 + .../amd/include/asic_reg/gc/gc_9_0_offset.h | 2 + .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 157 ++++ .../include/asic_reg/rsmu/rsmu_0_0_2_offset.h | 27 + .../asic_reg/rsmu/rsmu_0_0_2_sh_mask.h | 32 + .../include/asic_reg/umc/umc_6_1_1_offset.h | 31 + .../include/asic_reg/umc/umc_6_1_1_sh_mask.h | 91 ++ 20 files changed, 1967 insertions(+), 93 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_1.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
