On 7/25/19 1:40 PM, sunpeng.li@xxxxxxx wrote:
> From: Leo Li <sunpeng.li@xxxxxxx>
>
> Using a static int array will cause errors if the given dm_pp_clk_type
> is out-of-bounds. For robustness, use a switch table, with a default
> case to handle all invalid values.
>
> Signed-off-by: Leo Li <sunpeng.li@xxxxxxx>
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 38 +++++++++++++------
> 1 file changed, 26 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index 20e82c9f6d67..df1efb8238d6 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -152,18 +152,32 @@ static void get_default_clock_levels(
> static enum smu_clk_type dc_to_smu_clock_type(
> enum dm_pp_clock_type dm_pp_clk_type)
> {
> -#define DCCLK_MAP_SMUCLK(dcclk, smuclk) \
> - [dcclk] = smuclk
> -
> - static int dc_clk_type_map[] = {
> - DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DISPLAY_CLK, SMU_DISPCLK),
> - DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_ENGINE_CLK, SMU_GFXCLK),
> - DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_MEMORY_CLK, SMU_MCLK),
> - DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DCEFCLK, SMU_DCEFCLK),
> - DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_SOCCLK, SMU_SOCCLK),
> - };
> -
> - return dc_clk_type_map[dm_pp_clk_type];
> + enum smu_clk_type smu_clk_type = 0;
This shouldn't be 0, but an actual value from the enum.
Right now this modifies GFX clock if the clock is invalid, but we should
probably be returning SMU_CLK_COUNT instead.
Nicholas Kazlauskas
> +
> + switch (dm_pp_clk_type) {
> + case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
> + smu_clk_type = SMU_DISPCLK;
> + break;
> + case DM_PP_CLOCK_TYPE_ENGINE_CLK:
> + smu_clk_type = SMU_GFXCLK;
> + break;
> + case DM_PP_CLOCK_TYPE_MEMORY_CLK:
> + smu_clk_type = SMU_MCLK;
> + break;
> + case DM_PP_CLOCK_TYPE_DCEFCLK:
> + smu_clk_type = SMU_DCEFCLK;
> + break;
> + case DM_PP_CLOCK_TYPE_SOCCLK:
> + smu_clk_type = SMU_SOCCLK;
> + break;
> + default:
> + DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
> + dm_pp_clk_type);
> + smu_clk_type = 0;
> + break;
> + }
> +
> + return smu_clk_type;
> }
>
> static enum amd_pp_clock_type dc_to_pp_clock_type(
>
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