AMDGPU
On 7/24/19 10:41 AM, Koenig, Christian wrote:
> Am 24.07.19 um 16:32 schrieb Grodzovsky, Andrey:
>> On 7/24/19 10:25 AM, Koenig, Christian wrote:
>>> Am 24.07.19 um 16:10 schrieb Andrey Grodzovsky:
>>>> From: Shirish S <shirish.s@xxxxxxx>
>>>>
>>>> enables gpu_vm_support in dm and adds
>>>> AMDGPU_GEM_DOMAIN_GTT as supported domain
>>>>
>>>> v2:
>>>> Move BO placement logic into amdgpu_display_supported_domains
>>>>
>>>> v3:
>>>> Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains.
>>>>
>>>> Change-Id: If34300beaa60be2d36170b7b5b096ec644502b20
>>>> Signed-off-by: Shirish S <shirish.s@xxxxxxx>
>>>> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@xxxxxxx>
>>> Actually that doesn't look like a good idea to me.
>>>
>>> It is still perfectly possible (and wanted!) that the USWC flag was not
>>> set in the first place by userspace.
>>>
>>> Is that still checked somewhere?
>>>
>>> Regards,
>>> Christian.
>> Not sure I understand here, can you elaborate ?
> It's still possible that userspace doesn't set the USWC flag and there
> actually might be good reasons for that.
>
> Do we still have a check for this case somewhere?
>
> Christian.
I don't see how this relates patch in particular. AFAIK user space will
go through amdgpu_gem_create_ioctl which I didn't touch it and don't
force AMDGPU_GEM_CREATE_CPU_GTT_USWC there, we only force
AMDGPU_GEM_CREATE_CPU_GTT_USWC for FB console BO creation in
amdgpufb_create_pinned_object and amdgpu_mode_dumb_create.
Andrey
>
>
>> Andrey
>>
>>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 16 ++++++++++++++--
>>>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>>>> 2 files changed, 15 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>>> index 767ee699..23b8046 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>>> @@ -37,6 +37,7 @@
>>>> #include <drm/drm_edid.h>
>>>> #include <drm/drm_gem_framebuffer_helper.h>
>>>> #include <drm/drm_fb_helper.h>
>>>> +#include <drm/drm_cache.h>
>>>>
>>>> static void amdgpu_display_flip_callback(struct dma_fence *f,
>>>> struct dma_fence_cb *cb)
>>>> @@ -496,10 +497,21 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
>>>> uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
>>>> {
>>>> uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
>>>> + u64 uswc_flag = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>>>>
>>>> #if defined(CONFIG_DRM_AMD_DC)
>>>> - if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
>>>> - adev->flags & AMD_IS_APU &&
>>>> + /*
>>>> + * if amdgpu_bo_validate_uswc clears AMDGPU_GEM_CREATE_CPU_GTT_USWC it
>>>> + * means that USWC mappings
>>>> + * is not supported for this board. But this mapping is required
>>>> + * to avoid hang caused by placement of scanout BO in GTT on certain
>>>> + * APUs. So force the BO placement to VRAM in case this architecture
>>>> + * will not allow USWC mappings.
>>>> + */
>>>> + amdgpu_bo_validate_uswc(&uswc_flag);
>>>> +
>>>> + if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&
>>>> + adev->flags & AMD_IS_APU && uswc_flag &&
>>>> amdgpu_device_asic_has_dc_support(adev->asic_type))
>>>> domain |= AMDGPU_GEM_DOMAIN_GTT;
>>>> #endif
>>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> index 4922589..f0387ce1 100644
>>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>> @@ -686,7 +686,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>>>> */
>>>> if (adev->flags & AMD_IS_APU &&
>>>> adev->asic_type >= CHIP_CARRIZO &&
>>>> - adev->asic_type < CHIP_RAVEN)
>>>> + adev->asic_type <= CHIP_RAVEN)
>>>> init_data.flags.gpu_vm_support = true;
>>>>
>>>> if (amdgpu_dc_feature_mask & DC_FBC_MASK)
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