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Hi Evan,
1. the other clock type also will check dpm fine grained support. 2. i will change code to v2 to avoid below case 0: 300M *
Best Regards, Kevin From: Quan, Evan
Sent: Thursday, July 18, 2019 4:16:22 PM To: Wang, Kevin(Yang); amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Feng, Kenneth; Huang, Ray; Xu, Feifei Subject: RE: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10 1. Please commonilzie a new API e.g. smu_is_fine_grained_dpm which can be shared for other clocks in future.
2. if the current clock is same as min or max, the output will be a little strange 0: 300M * 1: 300M 2: 1800M Please check how raven handle this situation. Regards, Evan > -----Original Message----- > From: Wang, Kevin(Yang) <Kevin1.Wang@xxxxxxx> > Sent: Thursday, July 18, 2019 4:02 PM > To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Feng, Kenneth <Kenneth.Feng@xxxxxxx>; Quan, Evan > <Evan.Quan@xxxxxxx>; Huang, Ray <Ray.Huang@xxxxxxx>; Xu, Feifei > <Feifei.Xu@xxxxxxx>; Wang, Kevin(Yang) <Kevin1.Wang@xxxxxxx> > Subject: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for > navi10 > > the navi10 gfxclk (sclk) support fine grained DPM, > so use level 1 to show current dpm freq in sysfs pp_dpm_xxx > > Change-Id: Idae2424f8cc91fe94cebe7f3103e112b4f912fbc > Signed-off-by: Kevin Wang <kevin1.wang@xxxxxxx> > --- > drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 41 +++++++++++++++++-- > --- > 1 file changed, 33 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > index 895a4e592d5a..ef60b92fef6c 100644 > --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > @@ -632,6 +632,10 @@ static int navi10_print_clk_levels(struct smu_context > *smu, > { > int i, size = 0, ret = 0; > uint32_t cur_value = 0, value = 0, count = 0; > + uint32_t freq_values[3] = {0}; > + uint32_t clk_index = 0, mark_index = 0; > + PPTable_t *pptable = smu->smu_table.driver_pptable; > + DpmDescriptor_t *dpm_desc = NULL; > > switch (clk_type) { > case SMU_GFXCLK: > @@ -641,25 +645,46 @@ static int navi10_print_clk_levels(struct > smu_context *smu, > case SMU_UCLK: > case SMU_FCLK: > case SMU_DCEFCLK: > + clk_index = smu_clk_get_index(smu, clk_type); > + dpm_desc = &pptable->DpmDescriptor[clk_index]; > + > ret = smu_get_current_clk_freq(smu, clk_type, &cur_value); > if (ret) > return size; > - /* 10KHz -> MHz */ > - cur_value = cur_value / 100; > - > - size += sprintf(buf, "current clk: %uMhz\n", cur_value); > > ret = smu_get_dpm_level_count(smu, clk_type, &count); > if (ret) > return size; > > - for (i = 0; i < count; i++) { > - ret = smu_get_dpm_freq_by_index(smu, clk_type, i, > &value); > + /* 0 - Fine grained DPM, 1 - Discrete DPM */ > + if (dpm_desc->SnapToDiscrete == 1) { > + /* 10KHz -> MHz */ > + cur_value = cur_value / 100; > + for (i = 0; i < count; i++) { > + ret = smu_get_dpm_freq_by_index(smu, > clk_type, i, &value); > + if (ret) > + return size; > + > + size += sprintf(buf + size, "%d: %uMhz %s\n", > i, value, > + cur_value == value ? "*" : ""); > + } > + } else { > + ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, > &freq_values[0]); > + if (ret) > + return size; > + ret = smu_get_dpm_freq_by_index(smu, clk_type, > count - 1, &freq_values[2]); > if (ret) > return size; > > - size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, > - cur_value == value ? "*" : ""); > + freq_values[1] = cur_value / 100; > + mark_index = cur_value == freq_values[0] ? 0 : > + cur_value == freq_values[2] ? 2 : 1; > + > + for (i = 0; i < 3; i++) { > + size += sprintf(buf + size, "%d: %uMhz %s\n", > i, freq_values[i], > + i == mark_index ? "*" : ""); > + } > + > } > break; > default: > -- > 2.22.0 |
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