add mode1 (by psp) reset for navi asic.
Change-Id: Id2e7cb11eb7026296d1488c7c39f895b100f206c
Signed-off-by: Kevin Wang <kevin1.wang@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 35 +++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index f6f152e6ade4..05fd4736bc0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -256,6 +256,39 @@ static void nv_gpu_pci_config_reset(struct amdgpu_device *adev)
}
#endif
+static int nv_asic_mode1_reset(struct amdgpu_device *adev)
+{
+ u32 i;
+ int ret = 0;
+
+ amdgpu_atombios_scratch_regs_engine_hung(adev, true);
+
+ dev_info(adev->dev, "GPU mode1 reset\n");
+
+ /* disable BM */
+ pci_clear_master(adev->pdev);
+
+ pci_save_state(adev->pdev);
+
+ ret = psp_gpu_reset(adev);
+ if (ret)
+ dev_err(adev->dev, "GPU mode1 reset failed\n");
+
+ pci_restore_state(adev->pdev);
+
+ /* wait for asic to come out of reset */
+ for (i = 0; i < adev->usec_timeout; i++) {
+ u32 memsize = adev->nbio_funcs->get_memsize(adev);
+
+ if (memsize != 0xffffffff)
+ break;
+ udelay(1);
+ }
+
+ amdgpu_atombios_scratch_regs_engine_hung(adev, false);
+
+ return ret;
+}
static int nv_asic_reset(struct amdgpu_device *adev)
{
@@ -272,6 +305,8 @@ static int nv_asic_reset(struct amdgpu_device *adev)
if (smu_baco_is_support(smu)) {
ret = smu_baco_reset(smu);
+ } else {
+ ret = nv_asic_mode1_reset(adev);
}
return ret;
--
2.22.0
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