From: Boyuan Zhang <boyuan.zhang@xxxxxxx>
Set all jpeg encode ring function pointers.
Signed-off-by: Boyuan Zhang <boyuan.zhang@xxxxxxx>
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 38 +++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index b953f6422560..82a91f73e175 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -89,6 +89,7 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev);
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
+static void vcn_v2_0_set_jpeg_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v2_0_set_powergating_state(void *handle,
enum amd_powergating_state state);
@@ -109,6 +110,7 @@ static int vcn_v2_0_early_init(void *handle)
vcn_v2_0_set_dec_ring_funcs(adev);
vcn_v2_0_set_enc_ring_funcs(adev);
vcn_v2_0_set_jpeg_ring_funcs(adev);
+ vcn_v2_0_set_jpeg_enc_ring_funcs(adev);
vcn_v2_0_set_irq_funcs(adev);
return 0;
@@ -2108,6 +2110,36 @@ static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = {
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
};
+static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_enc_ring_vm_funcs = {
+ .type = AMDGPU_RING_TYPE_VCN_JPEG_ENC,
+ .align_mask = 0xf,
+ .vmhub = AMDGPU_MMHUB,
+ .get_rptr = vcn_v2_0_jpeg_enc_ring_get_rptr,
+ .get_wptr = vcn_v2_0_jpeg_enc_ring_get_wptr,
+ .set_wptr = vcn_v2_0_jpeg_enc_ring_set_wptr,
+ .emit_frame_size =
+ SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+ SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+ 8 + /* vcn_v2_0_jpeg_enc_ring_emit_vm_flush */
+ 18 + 18 + /* vcn_v2_0_jpeg_enc_ring_emit_fence x2 vm fence */
+ 8 + 16,
+ .emit_ib_size = 22, /* vcn_v2_0_jpeg_enc_ring_emit_ib */
+ .emit_ib = vcn_v2_0_jpeg_enc_ring_emit_ib,
+ .emit_fence = vcn_v2_0_jpeg_enc_ring_emit_fence,
+ .emit_vm_flush = vcn_v2_0_jpeg_enc_ring_emit_vm_flush,
+ //.test_ring
+ //.test_ib
+ .insert_nop = vcn_v2_0_jpeg_enc_ring_nop,
+ .insert_start = vcn_v2_0_jpeg_enc_ring_insert_start,
+ .insert_end = vcn_v2_0_jpeg_enc_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_vcn_ring_begin_use,
+ .end_use = amdgpu_vcn_ring_end_use,
+ .emit_wreg = vcn_v2_0_jpeg_enc_ring_emit_wreg,
+ .emit_reg_wait = vcn_v2_0_jpeg_enc_ring_emit_reg_wait,
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+};
+
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
{
adev->vcn.ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
@@ -2130,6 +2162,12 @@ static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
}
+static void vcn_v2_0_set_jpeg_enc_ring_funcs(struct amdgpu_device *adev)
+{
+ adev->vcn.ring_jpeg_enc.funcs = &vcn_v2_0_jpeg_enc_ring_vm_funcs;
+ DRM_INFO("VCN jpeg encode is enabled in VM mode\n");
+}
+
static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
.set = vcn_v2_0_set_interrupt_state,
.process = vcn_v2_0_process_interrupt,
--
2.17.1
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