Re: [PATCH 2/2] drm/amdgpu/gfx10: use reset default for PA_SC_FIFO_SIZE

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Reviewed-by: Xiaojie Yuan <xiaojie.yuan@xxxxxxx>

BR,
Xiaojie

________________________________________
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Alex Deucher <alexdeucher@xxxxxxxxx>
Sent: Monday, July 1, 2019 10:00 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdgpu/gfx10: use reset default for PA_SC_FIFO_SIZE

Recommended by the hw team.

Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2932ade7dbd0..ccd5a4968a60 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1544,24 +1544,6 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)

        gfx_v10_0_init_compute_vmid(adev);

-       mutex_lock(&adev->grbm_idx_mutex);
-       /*
-        * making sure that the following register writes will be broadcasted
-        * to all the shaders
-        */
-       gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-
-       tmp = REG_SET_FIELD(0, PA_SC_FIFO_SIZE, SC_FRONTEND_PRIM_FIFO_SIZE,
-                           adev->gfx.config.sc_prim_fifo_size_frontend);
-       tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_BACKEND_PRIM_FIFO_SIZE,
-                           adev->gfx.config.sc_prim_fifo_size_backend);
-       tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_HIZ_TILE_FIFO_SIZE,
-                           adev->gfx.config.sc_hiz_tile_fifo_size);
-       tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_EARLYZ_TILE_FIFO_SIZE,
-                           adev->gfx.config.sc_earlyz_tile_fifo_size);
-       WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, tmp);
-
-       mutex_unlock(&adev->grbm_idx_mutex);
 }

 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
--
2.20.1

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