Minor indentation and simplifications for the DF 3.6 driver. No
functional changes.
Signed-off-by: Tom St Denis <tom.stdenis@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 50 ++++++++++------------------
1 file changed, 18 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index e079ee066d87..21b214b2d652 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -27,8 +27,8 @@
#include "df/df_3_6_offset.h"
#include "df/df_3_6_sh_mask.h"
-static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
- 16, 32, 0, 0, 0, 2, 4, 8};
+static u32 df_v3_6_channel_number[] = { 1, 2, 0, 4, 0, 8, 0,
+ 16, 32, 0, 0, 0, 2, 4, 8};
static void df_v3_6_init(struct amdgpu_device *adev)
{
@@ -43,9 +43,10 @@ static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
- } else
+ } else {
WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
- mmFabricConfigAccessControl_DEFAULT);
+ mmFabricConfigAccessControl_DEFAULT);
+ }
}
static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
@@ -78,17 +79,13 @@ static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
/* Put DF on broadcast mode */
adev->df_funcs->enable_broadcast_mode(adev, true);
- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
- tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
- tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+ tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
+ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG))
tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
- WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
- } else {
- tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
- tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+ else
tmp |= DF_V3_6_MGCG_DISABLE;
- WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
- }
+ WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
/* Exit broadcast mode */
adev->df_funcs->enable_broadcast_mode(adev, false);
@@ -113,8 +110,8 @@ struct df_v3_6_event_mask {
/* get assigned df perfmon ctr as int */
static void df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev,
- uint64_t config,
- int *counter)
+ uint64_t config,
+ int *counter)
{
struct df_v3_6_event_mask *mask;
int i;
@@ -225,7 +222,6 @@ static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev,
int i, target_cntr;
target_cntr = -1;
-
*is_assigned = 0;
df_v3_6_pmc_config_2_cntr(adev, config, &target_cntr);
@@ -348,11 +344,11 @@ static int df_v3_6_add_xgmi_link_cntr(struct amdgpu_device *adev,
return ret;
ret = df_v3_6_pmc_get_ctrl_settings(adev,
- config,
- &lo_base_addr,
- &hi_base_addr,
- &lo_val,
- &hi_val);
+ config,
+ &lo_base_addr,
+ &hi_base_addr,
+ &lo_val,
+ &hi_val);
if (ret)
return ret;
@@ -379,20 +375,14 @@ static int df_v3_6_start_xgmi_link_cntr(struct amdgpu_device *adev,
{
uint32_t lo_base_addr, hi_base_addr, lo_val;
uint64_t config;
- int ret;
+ int ret = 0;
if (instance < 0 || instance > 1)
return -EINVAL;
if (is_enable) {
-
ret = df_v3_6_add_xgmi_link_cntr(adev, instance);
-
- if (ret)
- return ret;
-
} else {
-
config = GET_INSTANCE_CONFIG(instance);
df_v3_6_pmc_get_ctrl_settings(adev,
@@ -408,8 +398,6 @@ static int df_v3_6_start_xgmi_link_cntr(struct amdgpu_device *adev,
lo_val = RREG32_PCIE(lo_base_addr);
WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22));
-
- ret = 0;
}
return ret;
@@ -439,7 +427,6 @@ static int df_v3_6_stop_xgmi_link_cntr(struct amdgpu_device *adev,
df_v3_6_reset_xgmi_link_cntr(adev, instance);
df_v3_6_pmc_release_cntr(adev, config);
} else {
-
df_v3_6_pmc_get_ctrl_settings(adev,
config,
&lo_base_addr,
@@ -475,7 +462,6 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
if (ret)
return ret;
- ret = 0;
break;
default:
break;
--
2.21.0
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