Reviewed-by: Emily Deng <Emily.Deng@xxxxxxx>
>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
>Trigger Huang
>Sent: Monday, June 3, 2019 7:43 PM
>To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
>Cc: Huang, Trigger <Trigger.Huang@xxxxxxx>
>Subject: [PATCH] drm/amdgpu: Hardcode reg access using L1 security
>
>Under Vega10 SR-IOV VF, L1 register access mode should be enabled by
>default as the non-security VF will no longer be supported.
>
>Signed-off-by: Trigger Huang <Trigger.Huang@xxxxxxx>
>---
> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>index 31030f8..235548c 100644
>--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>@@ -451,19 +451,16 @@ void xgpu_ai_mailbox_put_irq(struct
>amdgpu_device *adev)
>
> static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev) {
>- uint32_t rlc_fw_ver = RREG32_SOC15(GC, 0,
>mmRLC_GPM_GENERAL_6);
>- uint32_t sos_fw_ver = RREG32_SOC15(MP0, 0,
>mmMP0_SMN_C2PMSG_58);
>-
> adev->virt.reg_access_mode =
>AMDGPU_VIRT_REG_ACCESS_LEGACY;
>
>- if (rlc_fw_ver >= 0x5d)
>- adev->virt.reg_access_mode |=
>AMDGPU_VIRT_REG_ACCESS_RLC;
>+ /* Enable L1 security reg access mode by defaul, as non-security VF
>+ * will no longer be supported.
>+ */
>+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC;
>
>- if (sos_fw_ver >= 0x80455)
>- adev->virt.reg_access_mode |=
>AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
>+ adev->virt.reg_access_mode |=
>AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
>
>- if (sos_fw_ver >= 0x8045b)
>- adev->virt.reg_access_mode |=
>AMDGPU_VIRT_REG_SKIP_SEETING;
>+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING;
> }
>
> const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
>--
>2.7.4
>
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