On 2019-05-24 3:12 p.m., Kim, Jonathan wrote:
> add pmu counters to monitor amdgpu device performance
>
> Change-Id: I8449f4ea824c411ee24a5b783ac066189b9de08e
> Signed-off-by: Jonathan Kim <jonathan.kim@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 370 +++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h | 37 +++
> 4 files changed, 413 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 11a651ff7f0d..90d4c5d299dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -54,7 +54,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
> amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
> amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
> amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
> - amdgpu_vm_sdma.o
> + amdgpu_vm_sdma.o amdgpu_pmu.o
>
> # add asic specific block
> amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 582f5635fcb2..51f479b357a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -61,6 +61,7 @@
>
> #include "amdgpu_xgmi.h"
> #include "amdgpu_ras.h"
> +#include "amdgpu_pmu.h"
>
> MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
> MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
> @@ -2748,6 +2749,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> goto failed;
> }
>
> + r = amdgpu_pmu_init(adev);
> + if (r)
> + dev_err(adev->dev, "amdgpu_pmu_init failed\n");
> +
> /* must succeed. */
> amdgpu_ras_resume(adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> new file mode 100644
> index 000000000000..b991e988d6fa
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> @@ -0,0 +1,370 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Author: Jonathan Kim <jonathan.kim@xxxxxxx>
> + *
> + */
> +
> +#define pr_fmt(fmt) "perf/amdgpu_pmu: " fmt
> +
> +#include <linux/perf_event.h>
> +#include <linux/init.h>
> +#include <linux/cpumask.h>
> +#include <linux/slab.h>
> +#include "amdgpu.h"
> +#include "amdgpu_pmu.h"
> +#include "df_v3_6.h"
> +
> +#define PMU_NAME_SIZE 32
> +
> +struct amdgpu_perf_status {
> + struct list_head list;
> + struct pmu pmu;
> + struct amdgpu_device *gpu;
> + int node_idx;
> + char name[PMU_NAME_SIZE];
> + u8 max_counters;
> + uint64_t cntr_assign_mask;
> + raw_spinlock_t lock;
> +};
> +
> +static LIST_HEAD(amdgpu_perf_status_list);
> +
> +
> +/*---------------------------------------------
> + * sysfs format attributes
> + *---------------------------------------------*/
> +
> +PMU_FORMAT_ATTR(df_event, "config:0-7");
> +PMU_FORMAT_ATTR(df_instance, "config:8-15");
> +PMU_FORMAT_ATTR(df_unitmask, "config:16-23");
> +
> +static struct attribute *amdgpu_pmu_format_attrs[] = {
> + &format_attr_df_event.attr,
> + &format_attr_df_instance.attr,
> + &format_attr_df_unitmask.attr,
> + NULL,
> +};
> +
> +
> +static struct attribute_group amdgpu_pmu_format_group = {
> + .name = "format",
> + .attrs = amdgpu_pmu_format_attrs,
> +};
> +
> +
> +/*---------------------------------------------
> + * sysfs events attributes
> + *---------------------------------------------*/
> +
> +
> +static struct attribute_group amdgpu_pmu_events_group = {
> + .name = "events",
> +};
> +
> +struct AMDGPU_PMU_EVENT_DESC {
> + struct kobj_attribute attr;
> + const char *event;
> +};
> +
> +static ssize_t _pmu_event_show(struct kobject *kobj,
> + struct kobj_attribute *attr, char *buf)
> +{
> + struct AMDGPU_PMU_EVENT_DESC *event =
> + container_of(attr, struct AMDGPU_PMU_EVENT_DESC, attr);
> + return sprintf(buf, "%s\n", event->event);
> +}
> +
> +#define AMDGPU_PMU_EVENT_DESC(_name, _event) \
> +{ \
> + .attr = __ATTR(_name, 0444, _pmu_event_show, NULL), \
> + .event = _event, \
> +}
> +
> +
> +/* DF event descriptors */
> +static struct AMDGPU_PMU_EVENT_DESC amdgpu_vega20_df_event_descs[] = {
> + AMDGPU_PMU_EVENT_DESC(cake0_pcsout_txdata,
> + "df_event=0x7,df_instance=0x46,df_unitmask=0x2"),
> + AMDGPU_PMU_EVENT_DESC(cake1_pcsout_txdata,
> + "df_event=0x7,df_instance=0x47,df_unitmask=0x2"),
> + AMDGPU_PMU_EVENT_DESC(cake0_pcsout_txmeta,
> + "df_event=0x7,df_instance=0x46,df_unitmask=0x4"),
> + AMDGPU_PMU_EVENT_DESC(cake1_pcsout_txmeta,
> + "df_event=0x7,df_instance=0x47,df_unitmask=0x4"),
> + AMDGPU_PMU_EVENT_DESC(cake0_ftiinstat_reqalloc,
> + "df_event=0xb,df_instance=0x46,df_unitmask=0x4"),
> + AMDGPU_PMU_EVENT_DESC(cake1_ftiinstat_reqalloc,
> + "df_event=0xb,df_instance=0x47,df_unitmask=0x4"),
> + AMDGPU_PMU_EVENT_DESC(cake0_ftiinstat_rspalloc,
> + "df_event=0xb,df_instance=0x46,df_unitmask=0x8"),
> + AMDGPU_PMU_EVENT_DESC(cake1_ftiinstat_rspalloc,
> + "df_event=0xb,df_instance=0x47,df_unitmask=0x8"),
> + { /* end: all zeroes */ },
> +};
> +
> +
> +/* Initialize PMU */
> +static int amdgpu_perf_event_init(struct perf_event *event)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> +
> + /* test the event attr type check for PMU enumeration */
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + /* update the hw_perf_event struct with config data */
> + hwc->conf = event->attr.config;
> +
> + return 0;
> +}
> +
> +/* Start PMU */
> +static void amdgpu_perf_start(struct perf_event *event, int flags)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> + struct amdgpu_device *adev = container_of(event->pmu,
> + struct amdgpu_perf_status, pmu)->gpu;
> +
> + if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
> + return;
> +
> + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
> + hwc->state = 0;
> +
> + if (!(flags & PERF_EF_RELOAD))
> + adev->df_funcs->pmc_start(adev, hwc->conf, 1);
> +
> + adev->df_funcs->pmc_start(adev, hwc->conf, 0);
> +
> + perf_event_update_userpage(event);
> +
> +}
> +
> +/* Read PMU */
> +static void amdgpu_perf_read(struct perf_event *event)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> + struct amdgpu_device *adev = container_of(event->pmu,
> + struct amdgpu_perf_status,
> + pmu)->gpu;
> +
> + u64 count, prev;
> +
> + adev->df_funcs->pmc_get_count(adev, hwc->conf, &count);
> +
> + prev = local64_read(&hwc->prev_count);
> + if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev)
> + return;
> +
> + local64_add(count - prev, &event->count);
> +}
> +
> +/* Stop PMU */
> +static void amdgpu_perf_stop(struct perf_event *event, int flags)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> + struct amdgpu_device *adev = container_of(event->pmu,
> + struct amdgpu_perf_status,
> + pmu)->gpu;
> +
> + if (hwc->state & PERF_HES_UPTODATE)
> + return;
> +
> + adev->df_funcs->pmc_stop(adev, hwc->conf, 0);
> +
> + WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
> + hwc->state |= PERF_HES_STOPPED;
> +
> + if (hwc->state & PERF_HES_UPTODATE)
> + return;
> +
> + amdgpu_perf_read(event);
> + hwc->state |= PERF_HES_UPTODATE;
> +}
> +
> +/* Add PMU */
> +static int amdgpu_perf_add(struct perf_event *event, int flags)
> +{
> +
> + struct hw_perf_event *hwc = &event->hw;
> + int retval;
> +
> + struct amdgpu_device *adev = container_of(event->pmu,
> + struct amdgpu_perf_status,
> + pmu)->gpu;
> +
> + event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
> +
> + adev->df_funcs->pmc_start(adev, hwc->conf, 1);
> +
> + if (retval)
> + return retval;
> +
> + if (flags & PERF_EF_START)
> + amdgpu_perf_start(event, PERF_EF_RELOAD);
> +
> + return retval;
> +
> +}
> +
> +/* Delete PMU */
> +static void amdgpu_perf_del(struct perf_event *event, int flags)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> +
> + struct amdgpu_device *adev = container_of(event->pmu,
> + struct amdgpu_perf_status,
> + pmu)->gpu;
> +
> + amdgpu_perf_stop(event, PERF_EF_UPDATE);
> +
> +
> + adev->df_funcs->pmc_stop(adev, hwc->conf, 1);
> +
> + perf_event_update_userpage(event);
> +}
> +
> +/* Initialize SYSFS attributes for AMDGPU PMU */
> +static int init_events_attrs(struct amdgpu_device *adev)
> +{
> + struct attribute **attrs;
> + int i = 0, j;
> +
> + switch (adev->asic_type) {
> + case CHIP_VEGA20:
> + while (amdgpu_vega20_df_event_descs[i].attr.attr.name)
> + i++;
> + break;
> + default:
> + break;
> + }
> +
> + attrs = kcalloc(i + 1, sizeof(struct attribute **), GFP_KERNEL);
> + if (!attrs)
> + return -ENOMEM;
> +
> + switch (adev->asic_type) {
> + case CHIP_VEGA20:
> + for (j = 0; j < i; j++)
> + attrs[j] = &amdgpu_vega20_df_event_descs[j].attr.attr;
> + break;
> + default:
> + break;
> + }
> +
> + amdgpu_pmu_events_group.attrs = attrs;
This is a per-device function modifying a global variable. That's
probably incorrect and it'll break on a multi-GPU system. The
amdgpu_pmu_events_group should be per-device, somewhere in adev.
Regards,
Felix
> + return 0;
> +}
> +
> +const struct attribute_group *amdgpu_pmu_attr_groups[] = {
> + &amdgpu_pmu_format_group,
> + &amdgpu_pmu_events_group,
> + NULL,
> +};
> +
> +
> +static const struct pmu amdgpu_pmu __initconst = {
> + .event_init = amdgpu_perf_event_init,
> + .add = amdgpu_perf_add,
> + .del = amdgpu_perf_del,
> + .start = amdgpu_perf_start,
> + .stop = amdgpu_perf_stop,
> + .read = amdgpu_perf_read,
> + .task_ctx_nr = perf_invalid_context,
> + .attr_groups = amdgpu_pmu_attr_groups,
> +};
> +
> +/* Initialize Data Fabric PMU */
> +static int init_df_pmu(struct amdgpu_device *adev)
> +{
> + struct amdgpu_perf_status *perf_status;
> + struct cntr_assign *c_assign;
> + int ret;
> +
> + perf_status = kzalloc(sizeof(struct amdgpu_perf_status), GFP_KERNEL);
> + if (!perf_status)
> + return -ENOMEM;
> +
> + raw_spin_lock_init(&perf_status->lock);
> +
> + /* initialize pmu and counters assignments */
> + perf_status->pmu = amdgpu_pmu;
> + perf_status->gpu = adev;
> + perf_status->max_counters = AMDGPU_DF_MAX_COUNTERS;
> + perf_status->node_idx = adev->ddev->primary->index;
> +
> + snprintf(perf_status->name, PMU_NAME_SIZE, "amdgpu_df_%d",
> + adev->ddev->primary->index);
> +
> + ret = perf_pmu_register(&perf_status->pmu, perf_status->name,
> + -1);
> +
> + if (!ret) {
> + pr_info("Detected AMDGPU DF Counters. # of Counters = %d.\n",
> + perf_status->max_counters);
> + list_add_tail(&perf_status->list, &amdgpu_perf_status_list);
> + } else {
> + pr_warn("Error initializing AMDGPU DF PMUs.\n");
> + kfree(perf_status);
> + }
> +
> + return ret;
> +}
> +
> +/* Initialize all PMU Blocks - Only DF for now */
> +static int init_pmu(struct amdgpu_device *adev)
> +{
> + int retval = 0;
> +
> + switch (adev->asic_type) {
> + case CHIP_VEGA20:
> + retval = init_df_pmu(adev);
> + break;
> + default: /* ignore all other chips */
> + break;
> + }
> +
> + return retval;
> +}
> +
> +
> +/* initialize AMDGPU PMU */
> +int amdgpu_pmu_init(struct amdgpu_device *adev)
> +{
> +
> + int ret;
> +
> + ret = init_events_attrs(adev);
> +
> + if (ret)
> + return ret;
> +
> + ret = init_pmu(adev);
> +
> + if (ret) {
> + kfree(amdgpu_pmu_events_group.attrs);
> + return -ENODEV;
> + }
> +
> + return ret;
> +}
> +
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
> new file mode 100644
> index 000000000000..d070d9e252ff
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
> @@ -0,0 +1,37 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Author: Jonathan Kim <jonathan.kim@xxxxxxx>
> + *
> + */
> +
> +#ifndef _AMDGPU_PMU_H_
> +#define _AMDGPU_PMU_H_
> +
> +enum amdgpu_pmu_perf_type {
> + PERF_TYPE_AMDGPU_DF = 0,
> + PERF_TYPE_AMDGPU_MAX
> +};
> +
> +
> +int amdgpu_pmu_init(struct amdgpu_device *adev);
> +
> +#endif /* _AMDGPU_PMU_H_ */
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
