On 2019-05-14 2:02 p.m., Kazlauskas, Nicholas wrote:
> On 5/14/19 1:49 PM, Harry Wentland wrote:
>>
>> [WHY]
>> These were only needed for bringup. They're not needed anymore.
>>
>> Signed-off-by: Harry Wentland <harry.wentland@xxxxxxx>
>
> Series is:
>
> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@xxxxxxx>
>
> I think a lot of those DCN guards around checking ASIC revision aren't
> strictly necessary (like the one in the first patch) and it seems kind
> of inconsistent between the files for what gets checked or not.
>
> This patch series seems fine to me though with the exception that
> there's not really a way for a user to get it back without patching
> their tree. Seems like that should almost be a configurable option for
> DC itself with the default to off for Raven.
>
We still have the DRM_AMD_DC_DCN1_0 guard as DCN-and-newer require
floating point support.
You're right in the DCN1_01 guard being inconsistent. I didn't want to
bother keeping it consistent in patch 1 and 2 as I was cleaning it here
anyways.
Harry
> Nicholas Kazlauskas
>
>> ---
>> drivers/gpu/drm/amd/display/Kconfig | 6 ------
>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 --
>> .../display/dc/bios/command_table_helper2.c | 5 -----
>> .../gpu/drm/amd/display/dc/core/dc_resource.c | 4 ----
>> .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 2 --
>> .../drm/amd/display/dc/dcn10/dcn10_resource.c | 19 -------------------
>> .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 ----
>> .../drm/amd/display/dc/gpio/hw_translate.c | 5 -----
>> .../gpu/drm/amd/display/include/dal_asic_id.h | 4 ----
>> .../gpu/drm/amd/display/include/dal_types.h | 2 --
>> 10 files changed, 53 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
>> index 13a6ce9c8e94..ed654a76c76a 100644
>> --- a/drivers/gpu/drm/amd/display/Kconfig
>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>> @@ -5,7 +5,6 @@ config DRM_AMD_DC
>> bool "AMD DC - Enable new display engine"
>> default y
>> select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
>> - select DRM_AMD_DC_DCN1_01 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
>> help
>> Choose this option if you want to use the new display engine
>> support for AMDGPU. This adds required support for Vega and
>> @@ -16,11 +15,6 @@ config DRM_AMD_DC_DCN1_0
>> help
>> RV family support for display engine
>>
>> -config DRM_AMD_DC_DCN1_01
>> - def_bool n
>> - help
>> - RV2 family for display engine
>> -
>> config DEBUG_KERNEL_DC
>> bool "Enable kgdb break in DC"
>> depends on DRM_AMD_DC
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 9f5e1e79ac8a..4a1755bce96c 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -666,10 +666,8 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
>> case CHIP_RAVEN:
>> if (ASICREV_IS_PICASSO(adev->external_rev_id))
>> fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
>> fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
>> -#endif
>> else
>> return 0;
>> break;
>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> index 8196f3bb10c7..53deba42007a 100644
>> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> @@ -57,11 +57,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>> return true;
>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>> case DCN_VERSION_1_0:
>> - *h = dal_cmd_tbl_helper_dce112_get_table2();
>> - return true;
>> -#endif
>> -
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> case DCN_VERSION_1_01:
>> *h = dal_cmd_tbl_helper_dce112_get_table2();
>> return true;
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> index 58ce7a6b914c..d9bfffb2c48d 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> @@ -93,10 +93,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>> case FAMILY_RV:
>> dc_version = DCN_VERSION_1_0;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
>> dc_version = DCN_VERSION_1_01;
>> -#endif
>> break;
>> #endif
>> default:
>> @@ -147,9 +145,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
>>
>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>> case DCN_VERSION_1_0:
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> case DCN_VERSION_1_01:
>> -#endif
>> res_pool = dcn10_create_resource_pool(init_data, dc);
>> break;
>> #endif
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
>> index 177247595974..bf978831bb0e 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
>> @@ -927,9 +927,7 @@ void hubbub1_construct(struct hubbub *hubbub,
>> hubbub1->masks = hubbub_mask;
>>
>> hubbub1->debug_test_index_pstate = 0x7;
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> if (ctx->dce_version == DCN_VERSION_1_01)
>> hubbub1->debug_test_index_pstate = 0xB;
>> -#endif
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> index ddb020a53098..dc7cf3704252 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>> @@ -152,9 +152,7 @@ enum dcn10_clk_src_array_id {
>> DCN10_CLK_SRC_PLL2,
>> DCN10_CLK_SRC_PLL3,
>> DCN10_CLK_SRC_TOTAL,
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
>> -#endif
>> };
>>
>> /* begin *********************
>> @@ -522,7 +520,6 @@ static const struct resource_caps res_cap = {
>> .num_ddc = 4,
>> };
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> static const struct resource_caps rv2_res_cap = {
>> .num_timing_generator = 3,
>> .num_opp = 3,
>> @@ -532,7 +529,6 @@ static const struct resource_caps rv2_res_cap = {
>> .num_pll = 3,
>> .num_ddc = 3,
>> };
>> -#endif
>>
>> static const struct dc_plane_cap plane_cap = {
>> .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
>> @@ -1270,11 +1266,9 @@ static bool construct(
>>
>> ctx->dc_bios->regs = &bios_regs;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> if (ctx->dce_version == DCN_VERSION_1_01)
>> pool->base.res_cap = &rv2_res_cap;
>> else
>> -#endif
>> pool->base.res_cap = &res_cap;
>> pool->base.funcs = &dcn10_res_pool_funcs;
>>
>> @@ -1291,10 +1285,8 @@ static bool construct(
>> /* max pipe num for ASIC before check pipe fuses */
>> pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> if (dc->ctx->dce_version == DCN_VERSION_1_01)
>> pool->base.pipe_count = 3;
>> -#endif
>> dc->caps.max_video_width = 3840;
>> dc->caps.max_downscale_ratio = 200;
>> dc->caps.i2c_speed_in_khz = 100;
>> @@ -1327,26 +1319,17 @@ static bool construct(
>> CLOCK_SOURCE_COMBO_PHY_PLL2,
>> &clk_src_regs[2], false);
>>
>> -#ifdef CONFIG_DRM_AMD_DC_DCN1_01
>> if (dc->ctx->dce_version == DCN_VERSION_1_0) {
>> pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
>> dcn10_clock_source_create(ctx, ctx->dc_bios,
>> CLOCK_SOURCE_COMBO_PHY_PLL3,
>> &clk_src_regs[3], false);
>> }
>> -#else
>> - pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
>> - dcn10_clock_source_create(ctx, ctx->dc_bios,
>> - CLOCK_SOURCE_COMBO_PHY_PLL3,
>> - &clk_src_regs[3], false);
>> -#endif
>>
>> pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> if (dc->ctx->dce_version == DCN_VERSION_1_01)
>> pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
>> -#endif
>>
>> pool->base.dp_clock_source =
>> dcn10_clock_source_create(ctx, ctx->dc_bios,
>> @@ -1386,7 +1369,6 @@ static bool construct(
>> memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
>> memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> if (dc->ctx->dce_version == DCN_VERSION_1_01) {
>> struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
>> struct dcn_ip_params *dcn_ip = dc->dcn_ip;
>> @@ -1397,7 +1379,6 @@ static bool construct(
>> dcn_soc->dram_clock_change_latency = 23;
>> dcn_ip->max_num_dpp = 3;
>> }
>> -#endif
>> if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
>> dc->dcn_soc->urgent_latency = 3;
>> dc->debug.disable_dmcu = true;
>> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
>> index c2028c4744a6..a610fae16280 100644
>> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
>> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
>> @@ -84,10 +84,6 @@ bool dal_hw_factory_init(
>> return true;
>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>> case DCN_VERSION_1_0:
>> - dal_hw_factory_dcn10_init(factory);
>> - return true;
>> -#endif
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> case DCN_VERSION_1_01:
>> dal_hw_factory_dcn10_init(factory);
>> return true;
>> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
>> index 236ca28784a9..77615146b96e 100644
>> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
>> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
>> @@ -84,11 +84,6 @@ bool dal_hw_translate_init(
>> dal_hw_translate_dcn10_init(translate);
>> return true;
>> #endif
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> - case DCN_VERSION_1_01:
>> - dal_hw_translate_dcn10_init(translate);
>> - return true;
>> -#endif
>>
>> default:
>> BREAK_TO_DEBUGGER();
>> diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>> index 072d8d7debf5..63c3e77159d9 100644
>> --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>> +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>> @@ -131,11 +131,9 @@
>> #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
>> #define RAVEN_A0 0x01
>> #define RAVEN_B0 0x21
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> /* DCN1_01 */
>> #define PICASSO_A0 0x41
>> #define RAVEN2_A0 0x81
>> -#endif
>> #define RAVEN1_F0 0xF0
>> #define RAVEN_UNKNOWN 0xFF
>>
>> @@ -143,10 +141,8 @@
>> #define RAVEN1_F0 0xF0
>> #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> #define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
>> #define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
>> -#endif /* DCN1_01 */
>>
>> #define FAMILY_RV 142 /* DCN 1*/
>>
>> diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
>> index f5bd869d4320..dabdbc0999d4 100644
>> --- a/drivers/gpu/drm/amd/display/include/dal_types.h
>> +++ b/drivers/gpu/drm/amd/display/include/dal_types.h
>> @@ -45,9 +45,7 @@ enum dce_version {
>> DCE_VERSION_12_1,
>> DCE_VERSION_MAX,
>> DCN_VERSION_1_0,
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> DCN_VERSION_1_01,
>> -#endif /* DCN1_01 */
>> DCN_VERSION_MAX
>> };
>>
>> --
>> 2.21.0
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@xxxxxxxxxxxxxxxxxxxxx
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>
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