On 4/15/19 10:00 AM, Deucher, Alexander wrote:
> Maybe mention that this fixes issues with stutter mode and 4k. With that,
> Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of
> hersen wu <hersenxs.wu@xxxxxxx>
> *Sent:* Monday, April 15, 2019 9:52 AM
> *To:* amd-gfx@xxxxxxxxxxxxxxxxxxxxx; Feng, Kenneth
> *Cc:* Wu, Hersen
> *Subject:* [PATCH] SWDEV-183622 4k@60hz dp monitor always flicking
> [WHY] clock unit mis-match between caller DC and SMU interface.
> dc pass lock in mhz. the same unit as smu. no covert is needed.
>
> [HOW] remove covert_10k_to_mhz in smu interface
>
> Signed-off-by: hersen wu <hersenxs.wu@xxxxxxx>
In addition to Alex's comments, you'll want to drop that SWDEV tag from
the patch title and probably name it something like:
drm/amd/powerplay: Fix clock units mismatch between DC and SMU
Some other minor nitpicks in the commit body too that can be fixed up:
- dc pass (c)lock in mhz:
- no co(n)vert is needed.
With all those fixed, this patch is:
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@xxxxxxx>
> ---
> .../gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 17 ++++++-----------
> 1 file changed, 6 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index f32e3d0aaea6..078613348e78 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -204,18 +204,13 @@ static int smu10_set_clock_limit(struct pp_hwmgr
> *hwmgr, const void *input)
> return 0;
> }
>
> -static inline uint32_t convert_10k_to_mhz(uint32_t clock)
> -{
> - return (clock + 99) / 100;
> -}
> -
> static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr,
> uint32_t clock)
> {
> struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
> *)(hwmgr->backend);
>
> if (smu10_data->need_min_deep_sleep_dcefclk &&
> - smu10_data->deep_sleep_dcefclk !=
> convert_10k_to_mhz(clock)) {
> - smu10_data->deep_sleep_dcefclk = convert_10k_to_mhz(clock);
> + smu10_data->deep_sleep_dcefclk != clock) {
> + smu10_data->deep_sleep_dcefclk = clock;
> smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetMinDeepSleepDcefclk,
> smu10_data->deep_sleep_dcefclk);
> @@ -228,8 +223,8 @@ static int smu10_set_hard_min_dcefclk_by_freq(struct
> pp_hwmgr *hwmgr, uint32_t c
> struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
> *)(hwmgr->backend);
>
> if (smu10_data->dcf_actual_hard_min_freq &&
> - smu10_data->dcf_actual_hard_min_freq !=
> convert_10k_to_mhz(clock)) {
> - smu10_data->dcf_actual_hard_min_freq =
> convert_10k_to_mhz(clock);
> + smu10_data->dcf_actual_hard_min_freq != clock) {
> + smu10_data->dcf_actual_hard_min_freq = clock;
> smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetHardMinDcefclkByFreq,
>
> smu10_data->dcf_actual_hard_min_freq);
> @@ -242,8 +237,8 @@ static int smu10_set_hard_min_fclk_by_freq(struct
> pp_hwmgr *hwmgr, uint32_t cloc
> struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
> *)(hwmgr->backend);
>
> if (smu10_data->f_actual_hard_min_freq &&
> - smu10_data->f_actual_hard_min_freq !=
> convert_10k_to_mhz(clock)) {
> - smu10_data->f_actual_hard_min_freq =
> convert_10k_to_mhz(clock);
> + smu10_data->f_actual_hard_min_freq != clock) {
> + smu10_data->f_actual_hard_min_freq = clock;
> smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_SetHardMinFclkByFreq,
>
> smu10_data->f_actual_hard_min_freq);
> --
> 2.17.1
>
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