Series is: Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx> > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of > Huang Rui > Sent: Monday, February 25, 2019 2:12 AM > To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Huang, Ray <Ray.Huang@xxxxxxx>; Zhang, Hawking > <Hawking.Zhang@xxxxxxx> > Subject: [PATCH 2/2] drm/amdgpu: use REG32_PCIE wrapper instead for psp > > This patch uses REG32_PCIE wrapper instead of writting pci_index2 and > reading > pci_data2 for psp. This sequence should be protected by pcie_idx_lock. > > Suggested-by: Hawking Zhang <Hawking.Zhang@xxxxxxx> > Signed-off-by: Huang Rui <ray.huang@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c > b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c > index 38deb57..54926a0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c > @@ -500,9 +500,7 @@ static bool psp_v3_1_smu_reload_quirk(struct > psp_context *psp) > struct amdgpu_device *adev = psp->adev; > uint32_t reg; > > - reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000; > - WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg); > - reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2); > + reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); > return (reg & > MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; } > > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
