This patch adds the function to set deep sleep dcefclk. It will be used on
display part.
Signed-off-by: Huang Rui <ray.huang@xxxxxxx>
Reviewed-by: Evan Quan <evan.quan@xxxxxxx>
Reviewed-by: Kevin Wang <Kevin1.Wang@xxxxxxx>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 21 ++++++++++++++-------
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 6238b60..57975e1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -263,6 +263,7 @@ struct smu_funcs
int (*start_thermal_control)(struct smu_context *smu);
int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
void *data, uint32_t *size);
+ int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
};
#define smu_init_microcode(smu) \
@@ -358,6 +359,8 @@ struct smu_funcs
((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
#define smu_get_unallowed_feature_mask(smu, feature_mask, num) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_unallowed_feature_mask? (smu)->ppt_funcs->get_unallowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
+#define smu_set_deep_sleep_dcefclk(smu, clk) \
+ ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 610bf0e..17da50f 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -601,21 +601,27 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
+{
+ int ret;
+
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_SetMinDeepSleepDcefclk, clk);
+ if (ret)
+ pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
+
+ return ret;
+}
+
static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
{
- int ret = 0;
struct smu_table_context *table_context = &smu->smu_table;
if (!table_context)
return -EINVAL;
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_SetMinDeepSleepDcefclk,
+ return smu_set_deep_sleep_dcefclk(smu,
table_context->boot_values.dcefclk / 100);
- if (ret)
- pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
-
- return ret;
}
static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
@@ -1150,6 +1156,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
.start_thermal_control = smu_v11_0_start_thermal_control,
.read_sensor = smu_v11_0_read_sensor,
+ .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
