I think it would be better to restrict max_pfn in general under SRIOV.
When the higher address space doesn't work for the CSA it will probably
cause problems elsewhere as well.
Christian.
Am 22.01.19 um 11:49 schrieb wentalou:
since vm_size enlarged to 0x40000 GB,
sriov need to put csa below AMDGPU_GMC_HOLE.
or amdgpu_vm_alloc_pts would receive saddr among AMDGPU_GMC_HOLE,
and result in a range fault interrupt IIRC.
Change-Id: I405a25a01d949f3130889b346f71bedad8ebcae7
Signed-off-by: Wenta Lou <Wentao.Lou@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 6 ++++--
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 ++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index dd3bd01..7a93c36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -26,8 +26,10 @@
uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
{
- uint64_t addr = min(adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT,
- AMDGPU_GMC_HOLE_START);
+ uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
+ /* sriov put csa below AMDGPU_GMC_HOLE */
+ if (amdgpu_sriov_vf(adev))
+ addr = min(addr, AMDGPU_GMC_HOLE_START);
addr -= AMDGPU_VA_RESERVED_SIZE;
addr = amdgpu_gmc_sign_extend(addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index f87f717..cf9ec28 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -707,8 +707,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
vm_size = min(vm_size, 1ULL << 40);
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
- dev_info.virtual_address_max =
- min(vm_size, AMDGPU_GMC_HOLE_START);
+ if (amdgpu_sriov_vf(adev))
+ dev_info.virtual_address_max = min(vm_size, AMDGPU_GMC_HOLE_START - AMDGPU_VA_RESERVED_SIZE);
+ else
+ dev_info.virtual_address_max = min(vm_size, AMDGPU_GMC_HOLE_START);
if (vm_size > AMDGPU_GMC_HOLE_START) {
dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
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