As the gfxclk for SMU11 can have at most 16 discrete levels. Change-Id: I0c6a8db8f40206a240286471c6f7b1fffef15ea2 Signed-off-by: Evan Quan <evan.quan@xxxxxxx> --- drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 9afd36a031a9..77200711abbe 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -92,7 +92,7 @@ enum dm_pp_clock_type { (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \ "Invalid" -#define DM_PP_MAX_CLOCK_LEVELS 8 +#define DM_PP_MAX_CLOCK_LEVELS 16 struct dm_pp_clock_levels { uint32_t num_levels; -- 2.20.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx