|
thanks Rex, done!
I only push it to amd-staging-drm-next, is this enough?
发件人: Zhu, Rex
发送时间: 2018年12月4日 17:26:36 收件人: Yin, Tianci (Rico); Zhang, Jerry; Li, Pauline; Teng, Rui; Liang, Prike; Zhu, Changfeng; Wang, Kevin(Yang); amd-gfx@xxxxxxxxxxxxxxxxxxxxx 主题: Re: [PATCH] drm/amd/powerplay: improve OD code robustness Please add Signed-off-by in the patch commit.
Except that,
Patch is
Reviewed-by: Rex Zhu <Rex.Zhu@xxxxxxx>
Best Regards Rex From: Yin, Tianci (Rico)
Sent: Tuesday, December 4, 2018 5:01 PM To: Zhu, Rex; Zhang, Jerry; Li, Pauline; Teng, Rui; Liang, Prike; Zhu, Changfeng; Wang, Kevin(Yang); amd-gfx@xxxxxxxxxxxxxxxxxxxxx Subject: 答复: [PATCH] drm/amd/powerplay: improve OD code robustness hi ,
a lower request system clock may cause gpu hang, add protection code to avoid this kind of issue, pls help to review.
thanks!
Rico |
From e043842962adb62cfa9b2abf9e291be6f36c99dd Mon Sep 17 00:00:00 2001
From: tianci yin <tianci.yin@xxxxxxx>
Date: Tue, 4 Dec 2018 16:07:18 +0800
Subject: [PATCH] drm/amd/powerplay: improve OD code robustness
add protection code to avoid lower frequency trigger over drive.
Change-Id: If2f51d27e1cc19f67a24816e121b19fadc38cfa4
Reviewed-by: Rex Zhu <Rex.Zhu@xxxxxxx>
Signed-off-by: Tianci Yin <tianci.yin@xxxxxxx>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 12 ++++++++----
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 12 ++++++++----
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 5dcd21d..13d779e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3589,8 +3589,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
}
if (i >= sclk_table->count) {
- data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
- sclk_table->dpm_levels[i-1].value = sclk;
+ if (sclk > sclk_table->dpm_levels[i-1].value) {
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+ sclk_table->dpm_levels[i-1].value = sclk;
+ }
} else {
/* TODO: Check SCLK in DAL's minimum clocks
* in case DeepSleep divider update is required.
@@ -3607,8 +3609,10 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
}
if (i >= mclk_table->count) {
- data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
- mclk_table->dpm_levels[i-1].value = mclk;
+ if (mclk > mclk_table->dpm_levels[i-1].value) {
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+ mclk_table->dpm_levels[i-1].value = mclk;
+ }
}
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index e2bc6e0..79c8624 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3266,8 +3266,10 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
}
if (i >= sclk_table->count) {
- data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
- sclk_table->dpm_levels[i-1].value = sclk;
+ if (sclk > sclk_table->dpm_levels[i-1].value) {
+ data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+ sclk_table->dpm_levels[i-1].value = sclk;
+ }
}
for (i = 0; i < mclk_table->count; i++) {
@@ -3276,8 +3278,10 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
}
if (i >= mclk_table->count) {
- data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
- mclk_table->dpm_levels[i-1].value = mclk;
+ if (mclk > mclk_table->dpm_levels[i-1].value) {
+ data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+ mclk_table->dpm_levels[i-1].value = mclk;
+ }
}
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
--
2.7.4
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