[PATCH 10/16] drm/amd/display: Re-arrange GFX9 fields

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From: Nevenko Stupar <Nevenko.Stupar@xxxxxxx>

For more clear usage in future

Signed-off-by: Nevenko Stupar <Nevenko.Stupar@xxxxxxx>
Reviewed-by: Tony Cheng <Tony.Cheng@xxxxxxx>
Acked-by: Leo Li <sunpeng.li@xxxxxxx>
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 7825e4b..9ddfe4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -358,15 +358,16 @@ union dc_tiling_info {
 	} gfx8;
 
 	struct {
+		enum swizzle_mode_values swizzle;
 		unsigned int num_pipes;
-		unsigned int num_banks;
+		unsigned int max_compressed_frags;
 		unsigned int pipe_interleave;
+
+		unsigned int num_banks;
 		unsigned int num_shader_engines;
 		unsigned int num_rb_per_se;
-		unsigned int max_compressed_frags;
 		bool shaderEnable;
 
-		enum swizzle_mode_values swizzle;
 		bool meta_linear;
 		bool rb_aligned;
 		bool pipe_aligned;
-- 
2.7.4

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