On Mon, Nov 26, 2018 at 12:29 PM Oak Zeng <ozeng@xxxxxxx> wrote: > > v2: Use enum definition instead of hardcoded value > > Change-Id: I04d22fb717ac50483c0835f160a2e860e344f358 > Signed-off-by: Oak Zeng <ozeng@xxxxxxx> > Suggested-by: Felix Kuehling <Felix.Kuehling@xxxxxxx> > Suggested-by: Alex Deucher <alexander.deucher@xxxxxxx> With a patch description added: Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 50 ++++++++++++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/soc15.c | 22 +++++++++++- > drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + > drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 33 ++++++++++++++++++ > 4 files changed, 105 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 719da32..2fc5713 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -392,6 +392,56 @@ struct amdgpu_doorbell { > u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ > }; > > +typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT > +{ > + /* Compute + GFX: 0~255 */ > + AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, > + AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, > + AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, > + AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, > + AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, > + AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, > + AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, > + AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, > + AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, > + AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, > + AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, > + AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, > + AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, > + AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, > + /* SDMA:256~335*/ > + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, > + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, > + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, > + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, > + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, > + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, > + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, > + AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, > + /* IH: 376~391 */ > + AMDGPU_VEGA20_DOORBELL_IH = 0x178, > + /* MMSCH: 392~407 > + * overlap the doorbell assignment with VCN as they are mutually exclusive > + * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD > + */ > + AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ > + AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, > + AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, > + AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, > + > + AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, > + AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, > + AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, > + AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, > + > + AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, > + AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, > + AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, > + AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, > + AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F, > + AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF > +} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT; > + > /* > * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space > */ > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c > index cae25dd..83624e1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c > @@ -616,6 +616,23 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs = > .init_doorbell_index = &vega10_doorbell_index_init, > }; > > +static const struct amdgpu_asic_funcs vega20_asic_funcs = > +{ > + .read_disabled_bios = &soc15_read_disabled_bios, > + .read_bios_from_rom = &soc15_read_bios_from_rom, > + .read_register = &soc15_read_register, > + .reset = &soc15_asic_reset, > + .set_vga_state = &soc15_vga_set_state, > + .get_xclk = &soc15_get_xclk, > + .set_uvd_clocks = &soc15_set_uvd_clocks, > + .set_vce_clocks = &soc15_set_vce_clocks, > + .get_config_memsize = &soc15_get_config_memsize, > + .flush_hdp = &soc15_flush_hdp, > + .invalidate_hdp = &soc15_invalidate_hdp, > + .need_full_reset = &soc15_need_full_reset, > + .init_doorbell_index = &vega20_doorbell_index_init, > +}; > + > static int soc15_common_early_init(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > @@ -633,11 +650,11 @@ static int soc15_common_early_init(void *handle) > adev->se_cac_rreg = &soc15_se_cac_rreg; > adev->se_cac_wreg = &soc15_se_cac_wreg; > > - adev->asic_funcs = &soc15_asic_funcs; > > adev->external_rev_id = 0xFF; > switch (adev->asic_type) { > case CHIP_VEGA10: > + adev->asic_funcs = &soc15_asic_funcs; > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | > AMD_CG_SUPPORT_GFX_MGLS | > AMD_CG_SUPPORT_GFX_RLC_LS | > @@ -661,6 +678,7 @@ static int soc15_common_early_init(void *handle) > adev->external_rev_id = 0x1; > break; > case CHIP_VEGA12: > + adev->asic_funcs = &soc15_asic_funcs; > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | > AMD_CG_SUPPORT_GFX_MGLS | > AMD_CG_SUPPORT_GFX_CGCG | > @@ -683,6 +701,7 @@ static int soc15_common_early_init(void *handle) > adev->external_rev_id = adev->rev_id + 0x14; > break; > case CHIP_VEGA20: > + adev->asic_funcs = &vega20_asic_funcs; > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | > AMD_CG_SUPPORT_GFX_MGLS | > AMD_CG_SUPPORT_GFX_CGCG | > @@ -705,6 +724,7 @@ static int soc15_common_early_init(void *handle) > adev->external_rev_id = adev->rev_id + 0x28; > break; > case CHIP_RAVEN: > + adev->asic_funcs = &soc15_asic_funcs; > if (adev->rev_id >= 0x8) > adev->external_rev_id = adev->rev_id + 0x81; > else if (adev->pdev->device == 0x15d8) > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h > index d37c57d..a66c8bf 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15.h > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h > @@ -59,4 +59,5 @@ int vega10_reg_base_init(struct amdgpu_device *adev); > int vega20_reg_base_init(struct amdgpu_device *adev); > > void vega10_doorbell_index_init(struct amdgpu_device *adev); > +void vega20_doorbell_index_init(struct amdgpu_device *adev); > #endif > diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c > index d13fc4f..edce413 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c > +++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c > @@ -54,4 +54,37 @@ int vega20_reg_base_init(struct amdgpu_device *adev) > return 0; > } > > +void vega20_doorbell_index_init(struct amdgpu_device *adev) > +{ > + adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ; > + adev->doorbell_index.mec_ring0 = AMDGPU_VEGA20_DOORBELL_MEC_RING0; > + adev->doorbell_index.mec_ring1 = AMDGPU_VEGA20_DOORBELL_MEC_RING1; > + adev->doorbell_index.mec_ring2 = AMDGPU_VEGA20_DOORBELL_MEC_RING2; > + adev->doorbell_index.mec_ring3 = AMDGPU_VEGA20_DOORBELL_MEC_RING3; > + adev->doorbell_index.mec_ring4 = AMDGPU_VEGA20_DOORBELL_MEC_RING4; > + adev->doorbell_index.mec_ring5 = AMDGPU_VEGA20_DOORBELL_MEC_RING5; > + adev->doorbell_index.mec_ring6 = AMDGPU_VEGA20_DOORBELL_MEC_RING6; > + adev->doorbell_index.mec_ring7 = AMDGPU_VEGA20_DOORBELL_MEC_RING7; > + adev->doorbell_index.userqueue_start = AMDGPU_VEGA20_DOORBELL_USERQUEUE_START; > + adev->doorbell_index.userqueue_end = AMDGPU_VEGA20_DOORBELL_USERQUEUE_END; > + adev->doorbell_index.gfx_ring0 = AMDGPU_VEGA20_DOORBELL_GFX_RING0; > + adev->doorbell_index.sdma_engine0 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0; > + adev->doorbell_index.sdma_engine1 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1; > + adev->doorbell_index.sdma_engine2 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2; > + adev->doorbell_index.sdma_engine3 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3; > + adev->doorbell_index.sdma_engine4 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4; > + adev->doorbell_index.sdma_engine5 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5; > + adev->doorbell_index.sdma_engine6 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6; > + adev->doorbell_index.sdma_engine7 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7; > + adev->doorbell_index.ih = AMDGPU_VEGA20_DOORBELL_IH; > + adev->doorbell_index.uvd_vce.uvd_ring0_1 = AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1; > + adev->doorbell_index.uvd_vce.uvd_ring2_3 = AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3; > + adev->doorbell_index.uvd_vce.uvd_ring4_5 = AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5; > + adev->doorbell_index.uvd_vce.uvd_ring6_7 = AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7; > + adev->doorbell_index.uvd_vce.vce_ring0_1 = AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1; > + adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3; > + adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5; > + adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7; > + adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1; > +} > > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx