Am 12.11.18 um 11:33 schrieb Rex Zhu:
Alloc_pte failed when the VA address located in
the higher arrange of 256T.
so reserve the csa buffer under 128T as a work around.
[ 122.979425] amdgpu 0000:03:00.0: va above limit (0xFFFFFFFFFFF1F >= 0x1000000000)
[ 122.987080] BUG: unable to handle kernel paging request at ffff880e1a79fff8
Signed-off-by: Rex Zhu <Rex.Zhu@xxxxxxx>
Well NAK, userspace wants to use the full address space below 128T for SVM.
The problem is rather that you incorrectly use amdgpu_csa_vaddr(). See
the code in amdgpu_driver_open_kms() how to do it correctly:
uint64_t csa_addr = amdgpu_csa_vaddr(adev) &
AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, &fpriv->vm,
adev->virt.csa_obj,
&fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
if (r)
goto error_vm;
Christian.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index fea4555..e2f325b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -36,9 +36,9 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
{
uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
- addr -= AMDGPU_VA_RESERVED_SIZE * id;
+ addr = min(addr, AMDGPU_GMC_HOLE_START);
- addr = amdgpu_gmc_sign_extend(addr);
+ addr -= (uint64_t)AMDGPU_VA_RESERVED_SIZE * id;
return addr;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 338a091..ea6a12a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -711,7 +711,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
dev_info.virtual_address_max =
- min(vm_size, AMDGPU_GMC_HOLE_START);
+ min(vm_size, AMDGPU_GMC_HOLE_START - adev->vm_manager.reserved_vm_size);
if (vm_size > AMDGPU_GMC_HOLE_START) {
dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
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