On 2018-10-18 5:59 p.m., wrote: > > Please include a patch description on 2 and 3, with that fixed, series is: > > Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx> > Reviewed-by: Felix Kuehling <Felix.Kuehling@xxxxxxx> > ------------------------------------------------------------------------ > *From:* Zhao, Yong > *Sent:* Thursday, October 18, 2018 5:13:04 PM > *To:* amd-gfx@xxxxxxxxxxxxxxxxxxxxx; brahma_sw_dev > *Cc:* Zhao, Yong > *Subject:* [PATCH 3/3] drm/amdkfd: Use functions from amdgpu for > setting up page table base > > Change-Id: I42eb2e41ce21b4a6ea0c8394dcc762ee92b2ca5e > Signed-off-by: Yong Zhao <Yong.Zhao@xxxxxxx> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > index 4b79639..223bbc1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > @@ -46,6 +46,7 @@ > #include "v9_structs.h" > #include "soc15.h" > #include "soc15d.h" > +#include "gmc_v9_0.h" > > /* HACK: MMHUB and GC both have VM-related register with the same > * names but different offsets. Define the MMHUB register we need here > @@ -59,11 +60,6 @@ > #define mmMMHUB_VM_INVALIDATE_ENG16_ACK 0x0705 > #define mmMMHUB_VM_INVALIDATE_ENG16_ACK_BASE_IDX 0 > > -#define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b > -#define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 > -#define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c > -#define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 > - > #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 > #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 > #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 > @@ -1018,9 +1014,7 @@ static void > set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, > * now, all processes share the same address space size, like > * on GFX8 and older. > */ > - WREG32(SOC15_REG_OFFSET(MMHUB, 0, > mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), > lower_32_bits(base)); > - WREG32(SOC15_REG_OFFSET(MMHUB, 0, > mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), > upper_32_bits(base)); > + mmhub_v1_0_setup_vm_pt_regs(adev, vmid, base); > > - WREG32(SOC15_REG_OFFSET(GC, 0, > mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); > - WREG32(SOC15_REG_OFFSET(GC, 0, > mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); > + gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, base); > } > -- > 2.7.4 > _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
