On Thu, Oct 18, 2018 at 6:41 AM Evan Quan <evan.quan@xxxxxxx> wrote:
>
> The UCLK is forced to highest at the start of display configuration
> change. Downgrade the UCLK from highest after display configuration change.
> Otherwise, we may see the UCLK stuck in the highest in some cases.
>
> Change-Id: I7ee6dd3cf6b4df30667e48576612b6af1a8e9184
> Signed-off-by: Evan Quan <evan.quan@xxxxxxx>
Acked-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index b4dbbb7c334c..6e0b2b8df455 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -2046,6 +2046,8 @@ static int vega20_notify_smc_display_config_after_ps_adjustment(
> {
> struct vega20_hwmgr *data =
> (struct vega20_hwmgr *)(hwmgr->backend);
> + struct vega20_single_dpm_table *dpm_table =
> + &data->dpm_table.mem_table;
> struct PP_Clocks min_clocks = {0};
> struct pp_display_clock_request clock_req;
> int ret = 0;
> @@ -2076,6 +2078,15 @@ static int vega20_notify_smc_display_config_after_ps_adjustment(
> }
> }
>
> + if (data->smu_features[GNLD_DPM_UCLK].enabled) {
> + dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
> + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinByFreq,
> + (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
> + "[SetHardMinFreq] Set hard min uclk failed!",
> + return ret);
> + }
> +
> return 0;
> }
>
> --
> 2.19.1
>
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