On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu <Rex.Zhu@xxxxxxx> wrote: > > HW CG feature will be enabled after hw ip initialized > > Signed-off-by: Rex Zhu <Rex.Zhu@xxxxxxx> Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx> > --- > drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 10 ---------- > 1 file changed, 10 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c > index ec14798..b6b62a7 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c > @@ -302,16 +302,6 @@ static int fiji_start_smu(struct pp_hwmgr *hwmgr) > hwmgr->avfs_supported = false; > } > > - /* To initialize all clock gating before RLC loaded and running.*/ > - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, > - AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE); > - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, > - AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE); > - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, > - AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE); > - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, > - AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE); > - > /* Setup SoftRegsStart here for register lookup in case > * DummyBackEnd is used and ProcessFirmwareHeader is not executed > */ > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
