Apart from Felix comments, Looks good for me, patch 2 ~ 8 are Reviewed-by: Junwei Zhang <Jerry.Zhang at amd.com> Patch 9 ~ 11 are Acked-by: Junwei Zhang <Jerry.Zhang at amd.com> On 09/10/2018 02:03 AM, Christian König wrote: > Hi everyone, > > Especially on Vega and Raven VM handling is rather inefficient while creating PTEs because we originally only supported 2 level page tables and implemented 4 level page tables on top of that. > > This patch set reworks quite a bit of that handling and adds proper iterator and tree walking functions which are then used to update PTEs more efficiently. > > A totally constructed test case which tried to map 2GB of VRAM on an unaligned address is reduced from 45ms down to ~20ms on my test system. > > As a very positive side effect this also adds support for 1GB giant VRAM pages additional to the existing 2MB huge pages on Vega/Raven and also enables all additional power of two values (2MB-2GB) for the L1. > > This could be beneficial for applications which allocate very huge amounts of memory because it reduces the overhead of page table walks by 50% (huge pages where 25%). > > Please comment and/or review, > Christian. > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx >
