Hello Alex Deucher,
The patch 5f152a572c10: "drm/radeon: use pcie functions for link
width" from Jun 25, 2018, leads to the following static checker
warning:
drivers/gpu/drm/radeon/cik.c:9646 cik_pcie_gen3_enable()
warn: dead code because of 'speed_cap == 21' and 'speed_cap != 21'
drivers/gpu/drm/radeon/cik.c
9499 static void cik_pcie_gen3_enable(struct radeon_device *rdev)
9500 {
9501 struct pci_dev *root = rdev->pdev->bus->self;
9502 enum pci_bus_speed speed_cap;
9503 int bridge_pos, gpu_pos;
9504 u32 speed_cntl, current_data_rate;
9505 int i;
9506 u16 tmp16;
9507
9508 if (pci_is_root_bus(rdev->pdev->bus))
9509 return;
9510
9511 if (radeon_pcie_gen2 == 0)
9512 return;
9513
9514 if (rdev->flags & RADEON_IS_IGP)
9515 return;
9516
9517 if (!(rdev->flags & RADEON_IS_PCIE))
9518 return;
9519
9520 speed_cap = pcie_get_speed_cap(root);
9521 if (speed_cap == PCI_SPEED_UNKNOWN)
9522 return;
9523
9524 if ((speed_cap != PCIE_SPEED_8_0GT) &&
9525 (speed_cap != PCIE_SPEED_5_0GT))
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
We added this condition
9526 return;
9527
9528 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9529 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
9530 LC_CURRENT_DATA_RATE_SHIFT;
9531 if (speed_cap == PCIE_SPEED_8_0GT) {
9532 if (current_data_rate == 2) {
9533 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
9534 return;
9535 }
9536 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
9537 } else if (speed_cap == PCIE_SPEED_5_0GT) {
9538 if (current_data_rate == 1) {
9539 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
9540 return;
9541 }
9542 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
9543 }
9544
9545 bridge_pos = pci_pcie_cap(root);
9546 if (!bridge_pos)
9547 return;
9548
9549 gpu_pos = pci_pcie_cap(rdev->pdev);
9550 if (!gpu_pos)
9551 return;
9552
9553 if (speed_cap == PCIE_SPEED_8_0GT) {
9554 /* re-try equalization if gen3 is not already enabled */
9555 if (current_data_rate != 2) {
9556 u16 bridge_cfg, gpu_cfg;
9557 u16 bridge_cfg2, gpu_cfg2;
9558 u32 max_lw, current_lw, tmp;
9559
9560 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
9561 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
9562
9563 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
9564 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
9565
9566 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
9567 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
9568
9569 tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9570 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
9571 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
9572
9573 if (current_lw < max_lw) {
9574 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9575 if (tmp & LC_RENEGOTIATION_SUPPORT) {
9576 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
9577 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
9578 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
9579 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
9580 }
9581 }
9582
9583 for (i = 0; i < 10; i++) {
9584 /* check status */
9585 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
9586 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
9587 break;
9588
9589 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
9590 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
9591
9592 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
9593 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
9594
9595 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9596 tmp |= LC_SET_QUIESCE;
9597 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9598
9599 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9600 tmp |= LC_REDO_EQ;
9601 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9602
9603 mdelay(100);
9604
9605 /* linkctl */
9606 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
9607 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
9608 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
9609 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
9610
9611 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
9612 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
9613 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
9614 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
9615
9616 /* linkctl2 */
9617 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
9618 tmp16 &= ~((1 << 4) | (7 << 9));
9619 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
9620 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
9621
9622 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
9623 tmp16 &= ~((1 << 4) | (7 << 9));
9624 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
9625 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9626
9627 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9628 tmp &= ~LC_SET_QUIESCE;
9629 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9630 }
9631 }
9632 }
9633
9634 /* set the link speed */
9635 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
9636 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
9637 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9638
9639 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
9640 tmp16 &= ~0xf;
9641 if (speed_cap == PCIE_SPEED_8_0GT)
9642 tmp16 |= 3; /* gen3 */
9643 else if (speed_cap == PCIE_SPEED_5_0GT)
9644 tmp16 |= 2; /* gen2 */
9645 else
9646 tmp16 |= 1; /* gen1 */
^^^^^^^^^^^^^^^^^^^^^
I guess gen1 is no longer supported.
9647 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9648
9649 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9650 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
9651 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9652
9653 for (i = 0; i < rdev->usec_timeout; i++) {
9654 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9655 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
9656 break;
9657 udelay(1);
9658 }
9659 }
regards,
dan carpenter
