Added vega20 overdrive support based on existing OD sysfs
APIs. However, the OD logics are simplified on vega20. So,
the behavior will be a little different and works only on
some limited levels.
V2: fix typo
fix commit description
revise error logs
add support for clock OD
Change-Id: I403cb38a95863db664cf06d030ac42a19bff6b33
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 30 ++
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 281 +++++++++++++++++-
2 files changed, 310 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index e2577518b9c6..30717b1cf38e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -474,6 +474,8 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
* in each power level within a power state. The pp_od_clk_voltage is used for
* this.
*
+ * < For Vega10 and previous ASICs >
+ *
* Reading the file will display:
*
* - a list of engine clock levels and voltages labeled OD_SCLK
@@ -491,6 +493,34 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
* "c" (commit) to the file to commit your changes. If you want to reset to the
* default power levels, write "r" (reset) to the file to reset them.
*
+ *
+ * < For Vega20 >
+ *
+ * Reading the file will display:
+ *
+ * - engine clock and voltage(offset) labeled OD_SCLK for minimum level,
+ * middle level and maximum level
+ *
+ * - memory clock and voltage(offset) labeled OD_MCLK for maximum level
+ * The voltage tuning for memory is not supported temporarily.
+ *
+ * - a list of valid ranges for sclk, mclk, and voltage offset labeled
+ * OD_RANGE
+ *
+ * To manually adjust these settings:
+ *
+ * - First select manual using power_dpm_force_performance_level
+ *
+ * - Enter a new value for each level by writing a string that contains
+ * "s/m level clock voltage(offset)" to the file. E.g., "s 0 500 20"
+ * will update level 0 sclk to be 500 MHz with voltage increased by 20mV
+ *
+ * - When you have edited all of the states as needed, write "c" (commit)
+ * to the file to commit your changes
+ *
+ * - If you want to reset to the default power levels, write "r" (reset)
+ * to the file to reset them
+ *
*/
static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index ececa2f7fe5f..891e2967b4a4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -2506,11 +2506,189 @@ static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
return 0;
}
+static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
+ enum PP_OD_DPM_TABLE_COMMAND type,
+ long *input, uint32_t size)
+{
+ struct vega20_hwmgr *data =
+ (struct vega20_hwmgr *)(hwmgr->backend);
+ struct vega20_od8_single_setting *od8_settings =
+ data->od8_settings.od8_settings_array;
+ OverDriveTable_t *od_table =
+ &(data->smc_state_table.overdrive_table);
+ struct pp_clock_levels_with_latency clocks;
+ int32_t input_index, input_clk, input_vol, i;
+ uint32_t tb_freq_offset, tb_vol_offset;
+ int ret;
+
+ PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
+ return -EINVAL);
+
+ switch (type) {
+ case PP_OD_EDIT_SCLK_VDDC_TABLE:
+ if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
+ pr_info("Sclk voltage overdrive not supported\n");
+ return 0;
+ }
+
+ ret = vega20_get_sclks(hwmgr, &clocks);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Attempt to get gfx clk levels failed!",
+ return ret);
+
+ for (i = 0; i < size; i += 3) {
+ if (i + 3 > size) {
+ pr_info("invalid number of input parameters %d\n",
+ size);
+ return 0;
+ }
+
+ input_index = input[i];
+ input_clk = input[i + 1];
+ input_vol = input[i + 2];
+
+ if (input_index == 0) {
+ tb_freq_offset = OD8_SETTING_GFXCLK_FREQ1;
+ tb_vol_offset = OD8_SETTING_GFXCLK_VOLTAGE1;
+ } else if (input_index == clocks.num_levels / 2) {
+ tb_freq_offset = OD8_SETTING_GFXCLK_FREQ2;
+ tb_vol_offset = OD8_SETTING_GFXCLK_VOLTAGE2;
+ } else if (input_index == clocks.num_levels - 1) {
+ tb_freq_offset = OD8_SETTING_GFXCLK_FREQ3;
+ tb_vol_offset = OD8_SETTING_GFXCLK_VOLTAGE3;
+ } else {
+ pr_info("Setting for level %d is not supported\n",
+ input_index);
+ pr_info("Supported levels are: 0 %d %d\n",
+ clocks.num_levels / 2,
+ clocks.num_levels - 1);
+ return -EINVAL;
+ }
+
+ if (input_clk < od8_settings[tb_freq_offset].min_value ||
+ input_clk > od8_settings[tb_freq_offset].max_value) {
+ pr_info("clock freq %d is not within allowed range [%d - %d]\n",
+ input_clk,
+ od8_settings[tb_freq_offset].min_value,
+ od8_settings[tb_freq_offset].max_value);
+ return -EINVAL;
+ }
+
+ if (input_vol < od8_settings[tb_vol_offset].min_value ||
+ input_vol > od8_settings[tb_vol_offset].max_value) {
+ pr_info("clock voltage offset %d is not within allowed range [%d - %d]\n",
+ input_vol,
+ od8_settings[tb_vol_offset].min_value,
+ od8_settings[tb_vol_offset].max_value);
+ return -EINVAL;
+ }
+
+ if (input_index == 0) {
+ od_table->GfxclkFmin = input_clk;
+ od_table->GfxclkFreq1 = input_clk;
+ od_table->GfxclkOffsetVolt1 = input_vol;
+ } else if (input_index == clocks.num_levels / 2) {
+ od_table->GfxclkFreq2 = input_clk;
+ od_table->GfxclkOffsetVolt2 = input_vol;
+ } else {
+ od_table->GfxclkFmax = input_clk;
+ od_table->GfxclkFreq3 = input_clk;
+ od_table->GfxclkOffsetVolt3 = input_vol;
+ }
+ }
+ break;
+
+ case PP_OD_EDIT_MCLK_VDDC_TABLE:
+ if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
+ pr_info("Mclk voltage overdrive not supported\n");
+ return 0;
+ }
+
+ ret = vega20_get_memclocks(hwmgr, &clocks);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Attempt to get memory clk levels failed!",
+ return ret);
+
+ for (i = 0; i < size; i += 3) {
+ if (i + 3 > size) {
+ pr_info("invalid number of input parameters %d\n",
+ size);
+ return 0;
+ }
+
+ input_index = input[i];
+ input_clk = input[i + 1];
+ input_vol = input[i + 2];
+
+ if (input_index != clocks.num_levels - 1) {
+ pr_info("Setting for level %d is not supported\n",
+ input_index);
+ pr_info("Supported level is: %d\n",
+ clocks.num_levels - 1);
+ return -EINVAL;
+ }
+
+ if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
+ input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
+ pr_info("clock freq %d is not within allowed range [%d - %d]\n",
+ input_clk,
+ od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
+ od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
+ return -EINVAL;
+ }
+
+ if (input_vol != 0) {
+ pr_info("memory voltage offset has to be 0\n");
+ return -EINVAL;
+ }
+
+ od_table->UclkFmax = input_clk;
+ }
+
+ break;
+
+ case PP_OD_RESTORE_DEFAULT_TABLE:
+ ret = vega20_copy_table_from_smc(hwmgr,
+ (uint8_t *)od_table,
+ TABLE_OVERDRIVE);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to export overdrive table!",
+ return ret);
+ break;
+
+ case PP_OD_COMMIT_DPM_TABLE:
+ ret = vega20_copy_table_to_smc(hwmgr,
+ (uint8_t *)od_table,
+ TABLE_OVERDRIVE);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Failed to import overdrive table!",
+ return ret);
+
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
{
- int i, now, size = 0;
+ struct vega20_hwmgr *data =
+ (struct vega20_hwmgr *)(hwmgr->backend);
+ struct vega20_od8_single_setting *od8_settings =
+ data->od8_settings.od8_settings_array;
+ OverDriveTable_t *od_table =
+ &(data->smc_state_table.overdrive_table);
struct pp_clock_levels_with_latency clocks;
+ int i, now, size = 0;
int ret = 0;
switch (type) {
@@ -2551,6 +2729,105 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
case PP_PCIE:
break;
+ case OD_SCLK:
+ if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
+
+ ret = vega20_get_sclks(hwmgr, &clocks);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Attempt to get gfx clk levels failed!",
+ return ret);
+
+ size = sprintf(buf, "%s:\n", "OD_SCLK");
+ size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
+ od_table->GfxclkFreq1,
+ od_table->GfxclkOffsetVolt1);
+ size += sprintf(buf + size, "%d: %10uMhz %10dmV\n",
+ clocks.num_levels / 2,
+ od_table->GfxclkFreq2,
+ od_table->GfxclkOffsetVolt2);
+ size += sprintf(buf + size, "%d: %10uMhz %10dmV\n",
+ clocks.num_levels - 1,
+ od_table->GfxclkFreq3,
+ od_table->GfxclkOffsetVolt3);
+ }
+ break;
+
+ case OD_MCLK:
+ if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
+ ret = vega20_get_memclocks(hwmgr, &clocks);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Attempt to get memory clk levels failed!",
+ return ret);
+
+ size = sprintf(buf, "%s:\n", "OD_MCLK");
+ size += sprintf(buf + size, "%d: %10uMhz %10dmV\n",
+ clocks.num_levels - 1,
+ od_table->UclkFmax,
+ 0);
+ }
+
+ break;
+
+ case OD_RANGE:
+ if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
+
+ ret = vega20_get_sclks(hwmgr, &clocks);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Attempt to get gfx clk levels failed!",
+ return ret);
+
+
+ size = sprintf(buf, "%s:\n", "OD_RANGE");
+ size += sprintf(buf + size, "SCLK[0]: %7uMhz %10uMhz\n",
+ od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
+ od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
+ size += sprintf(buf + size, "VDDC[0]: %7dmV %11dmV\n",
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
+ size += sprintf(buf + size, "SCLK[%d]: %7uMhz %10uMhz\n",
+ clocks.num_levels / 2,
+ od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
+ od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
+ size += sprintf(buf + size, "VDDC[%d]: %7dmV %11dmV\n",
+ clocks.num_levels / 2,
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
+ size += sprintf(buf + size, "SCLK[%d]: %7uMhz %10uMhz\n",
+ clocks.num_levels - 1,
+ od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
+ od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
+ size += sprintf(buf + size, "VDDC[%d]: %7dmV %11dmV\n",
+ clocks.num_levels - 1,
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
+ od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
+ }
+
+ if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
+ ret = vega20_get_memclocks(hwmgr, &clocks);
+ PP_ASSERT_WITH_CODE(!ret,
+ "Attempt to get memory clk levels failed!",
+ return ret);
+
+ size += sprintf(buf + size, "SCLK[%d]: %7uMhz %10uMhz\n",
+ clocks.num_levels - 1,
+ od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value,
+ od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
+ size += sprintf(buf + size, "VDDMEM[%d]: %7dmV %11dmV\n",
+ clocks.num_levels - 1,
+ 0,
+ 0);
+ }
+ break;
default:
break;
}
@@ -3162,6 +3439,8 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
vega20_get_mclk_od,
.set_mclk_od =
vega20_set_mclk_od,
+ .odn_edit_dpm_table =
+ vega20_odn_edit_dpm_table,
/* for sysfs to retrive/set gfxclk/memclk */
.force_clock_level =
vega20_force_clock_level,
--
2.18.0
