On 08/28/2018 09:56 AM, Zhang, Jerry (Junwei) wrote: > On 08/28/2018 12:53 AM, Christian König wrote: >> Only use the lower address space on GMC9 for the system domain. >> Otherwise we would need to sign extend GMC addresses. >> >> Signed-off-by: Christian König <christian.koenig at amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++---- >> 1 file changed, 3 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> index e44b5191735d..d982956c8329 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) >> if (r) >> return r; >> >> - /* Set the internal MC address mask >> - * This is the max address of the GPU's >> - * internal address space. >> + /* Use only the lower range for the internal MC address mask. This is >> + * the max address of the GPU's internal address space. >> */ >> - adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ >> + adev->gmc.mc_mask = 0x7fffffffffffULL; > > do we need to update vm_size as 128T at the same time? Likely no, since we use that for system domain only. BTW, how do we decide it's size limitation. looks we always use that less than 40bit? Jerry > > Jerry > >> >> /* set DMA mask + need_dma32 flags. >> * PCIE - can handle 44-bits. >> > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
