Used wrong pp interface, the original interface is
exposed by dpm on SI and paritial CI.
Pointed out by Francis David <david.francis at amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index e5c5b0a..85b72d459 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -480,12 +480,17 @@ void pp_rv_set_display_requirement(struct pp_smu *pp,
{
const struct dc_context *ctx = pp->dm;
struct amdgpu_device *adev = ctx->driver_context;
+ void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- if (!pp_funcs || !pp_funcs->display_configuration_changed)
+ if (!req || !pp_funcs || !pp_funcs->display_configuration_changed)
return;
- amdgpu_dpm_display_configuration_changed(adev);
+ adev->pm.pm_display_cfg.min_dcef_deep_sleep_set_clk = req->min_deep_sleep_dcefclk_mhz/10;
+ adev->pm.pm_display_cfg.min_dcef_set_clk = req->hard_min_dcefclk_khz/10;
+ adev->pm.pm_display_cfg.num_display = req->display_count;
+ adev->pm.pm_display_cfg.min_core_set_clock = req->hard_min_fclk_khz/10;
+ pp_funcs->display_configuration_change(pp_handle, &adev->pm.pm_display_cfg);
}
void pp_rv_set_wm_ranges(struct pp_smu *pp,
--
1.9.1
